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Microchip downscaling has been one of the main drivers on the semiconductor industry to enable faster, more efficient, and compact microchips, greatly broadening their range of applications, like the Internet of Things, smart mobility, artificial intelligence and 5G, among others. Aside from transistor scaling, the Back End of Line (BEOL) interconnection network, which transfers power and signals from and into the transistors, must also be scaled down consequently. The scaling requirements have surpassed the maximum resolution achievable by any lithographic technique by solely relying on direct printing. In the case of low numerical aperture, Extreme UV (low NA EUV), the most advanced, commercially available lithography technology, printing line/space structures below pitch 30nm (P30) is extremely challenging. However, 3nm and newer nodes require BEOL line space structures with P26nm or narrower, in particular for the M2 layer. It is here where multipatterning techniques come into play. Self-Aligned multipatterning techniques allow to divide by a factor of two (double patterning, SADP), four (quadruple patterning, SAQP) or even eight (octuple patterning, SAOP) the pitch printed at lithography level, easing the lithography requirements. However, with multipatterning, there comes a risk that not all interconnect lines would be patterned with equal dimensions, which would introduce resistance and capacitance variations across lines that theoretically should be equivalent. Hence, all multipatterning techniques require a precise control of each of the fabrication steps to guarantee that all lines and spaces present the same dimensions, i.e., a balanced patterning with no pitch walking. The target of our work is to find the fabrication parameters that lead to the lowest pitch walking, roughness and defectivity conditions on EUV SADP patterning (eSADP) at P21nm structures with 10.5nm metal line Critical Dimension (CD). Thus, we carried out a set of experiments where the printed lithography line CD and the spacer thickness values are swept on 300mm silicon wafers. Then, we analyze the patterning performance at different stages of fabrication to see the evolution of line and space CDs, roughness and defectivity values to determine the best candidate for P2 nm eSADP patterning.
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