Low-power off-chip capacitor-free LDO design with high transient response

Haoran Wu; Jiayu Yin; Xindong Huang; Chengying Chen

doi:10.1117/12.3017372

15 January 2024 Low-power off-chip capacitor-free LDO design with high transient response

Haoran Wu, Jiayu Yin, Xindong Huang, Chengying Chen

Proceedings Volume 12983, Second International Conference on Electrical, Electronics, and Information Engineering (EEIE 2023); 129830X (2024) https://doi.org/10.1117/12.3017372
Event: Second International Conference on Electrical, Electronics, and Information Engineering (EEIE 2023), 2023, Wuhan, China

Abstract

To reduce the area occupied by the low dropout regulator (LDO) in the whole chip system and to current consumption in standby state, this paper proposes a new structure using a diode-connected PMOS as a load resistor, which optimizes the area of the chip under the premise of guaranteeing the performance. The circuit is realized with UMC 28nm 1p9m process. The simulation results show that it can stably output a voltage of 1.197V under an input voltage of 2.5-3.6V, and its current operation range is 100μA-20mA with a transient response time of ≤0.5μs, a quiescent current of 9μA, and a phase margin of ≥77°

(2024) Published by SPIE. Downloading of the abstract is permitted for personal use only.

Citation Download Citation

Haoran Wu, Jiayu Yin, Xindong Huang, and Chengying Chen "Low-power off-chip capacitor-free LDO design with high transient response", Proc. SPIE 12983, Second International Conference on Electrical, Electronics, and Information Engineering (EEIE 2023), 129830X (15 January 2024); https://doi.org/10.1117/12.3017372

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