Practical implementation of top-surface imaging process by silylation to sub-0.20-um lithography

Byung-Jun Park; Ki-Ho Baik; Hyoung-Gi Kim; Jin-Woong Kim; Cheol-Kyu Bok; Johan Vertommen; Rik Rosenlund

doi:10.1117/12.275843

7 July 1997 Practical implementation of top-surface imaging process by silylation to sub-0.20-μm lithography

Byung-Jun Park, Ki-Ho Baik, Hyoung-Gi Kim, Jin-Woong Kim, Cheol-Kyu Bok, Johan Vertommen, Rik Rosenlund

Proceedings Volume 3049, Advances in Resist Technology and Processing XIV; (1997) https://doi.org/10.1117/12.275843
Event: Microlithography '97, 1997, Santa Clara, CA, United States

Abstract

Top-surface imaging process by silylation (TIPS) has been suggested as an attractive solution to cope not only with limitation of resolution and process latitudes but also with line width variations due to reflections over steps. However this technique has not received a wide acceptance as a production worthy process until now, because of the stringent requirements on suitable silylation and dry development equipment that have good uniformity and good reproducibility. In a parametric study of TIPS dry development steps, we found the most important factors in the first step and the second step respectively. The optimized process demonstrated good etch rate uniformity and excellent 0.17 micrometer dense and isolated pattern of gate and islands pattern of capacitor in 1 G bit DRAM device. Their profiles were vertical and uniform within a wafer, while the proximity effect between dense and isolated pattern of gate remained 0.01 micrometer. In islands pattern, wider process margins of both local depth of focus (LDOF) and exposure latitude (EL) could be obtained and excellent 3(sigma) value of critical dimension (CD) uniformity within a wafer confirmed better applicability to 1 G bit DRAM and beyond. When silylated resist patten was transferred into substrate layer CD bias and uniformity could be controlled less than 0.02 micrometer. There were also no residues after both photoresist strip and induced polymer removal step. From these studies. TIPS process using cluster tool of silylation system made by LRC and TCP^TM9400^TMSE etcher for dry development was demonstrated a production worth process for the sub-0.20 micrometer lithography in terms of obtaining finer pattern without pattern problems and a reliable process for 1 G bit DRAM and beyond.

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Byung-Jun Park, Ki-Ho Baik, Hyoung-Gi Kim, Jin-Woong Kim, Cheol-Kyu Bok, Johan Vertommen, and Rik Rosenlund "Practical implementation of top-surface imaging process by silylation to sub-0.20-μm lithography", Proc. SPIE 3049, Advances in Resist Technology and Processing XIV, (7 July 1997); https://doi.org/10.1117/12.275843

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KEYWORDS

Etching

Photoresist materials

Semiconducting wafers

Lithography

Photoresist developing

Plasma

Critical dimension metrology

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