Application of alternating phase-shifting mask to 0.16 um CMOS logic gate patterns

Koji Matsuoka; Akio Misaka

doi:10.1117/12.275975

7 July 1997 Application of alternating phase-shifting mask to 0.16 μm CMOS logic gate patterns

Koji Matsuoka, Akio Misaka

Proceedings Volume 3051, Optical Microlithography X; (1997) https://doi.org/10.1117/12.275975
Event: Microlithography '97, 1997, Santa Clara, CA, United States

Abstract

An application of alternating phase-shifting mask to 0.16 micrometers logic gate patterns is studied. A double exposure method using positive resist in KrF excimer laser lithography is applied to obtain random gate patterns. To optimize the exposure conditions, proximity effects for 0.16 micrometers line patterns under various combinations of NA and (sigma) are examined using an aerial image simulator. To control the linewidth in +/- 10% CD, mask bias according to the space width and the mask pattern with two adjacent apertures which transfers an isolated line are applied. By using these techniques, 0.16 micrometers logic gate patterns including SRAM are demonstrated.

Citation Download Citation

Koji Matsuoka and Akio Misaka "Application of alternating phase-shifting mask to 0.16 μm CMOS logic gate patterns", Proc. SPIE 3051, Optical Microlithography X, (7 July 1997); https://doi.org/10.1117/12.275975

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