Parasitic resistance analysis for deep submicron CMOS with inverse modeling

Manabu Deura; Seiichiro Yamaguchi; Toshihiro Sugii

doi:10.1117/12.323983

4 September 1998 Parasitic resistance analysis for deep submicron CMOS with inverse modeling

Manabu Deura, Seiichiro Yamaguchi, Toshihiro Sugii

Proceedings Volume 3506, Microelectronic Device Technology II; (1998) https://doi.org/10.1117/12.323983
Event: Microelectronic Manufacturing, 1998, Santa Clara, CA, United States

Abstract

Reducing parasitic series resistance is an important issue for producing deep-submicron high-speed CMOS. Some valuable methods for determining parasitic resistance have been developed. However the extracted parasitic resistance for the pMOS (1000 (Omega) (mu) m) is much larger than rough estimation base of extension sheet resistance, silicide-bulk contact resistance and silicide sheet resistance would indicate. This paper described the inverse modeling technique to determine the active doping profile from measured CV and IV characteristics. We found that contribution of extension profile to the parasitic resistance was about 80% and the rest was caused by silicide-bulk contact resistance. The reason is that only 5% of implanted boron was activated. For more complete activation, a higher RTA temperature is effective. RTA at a temperature of 1050 degrees Celsius for 5 seconds confirmed by spreading resistance measurements that the activation ratio was three times larger than that at a temperature of 1000 degrees Celsius for 10 seconds. Consequently a parasitic resistance reduction of 100 (Omega) can be expected by using the higher temperature process.

Citation Download Citation

Manabu Deura, Seiichiro Yamaguchi, and Toshihiro Sugii "Parasitic resistance analysis for deep submicron CMOS with inverse modeling", Proc. SPIE 3506, Microelectronic Device Technology II, (4 September 1998); https://doi.org/10.1117/12.323983

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