Influence of floating gate tungsten polycide deposition technique on EEPROM electrical characteristics

Karine Ogier-Monnier; Philippe Boivin; Olivier Bonnaud

doi:10.1117/12.324339

3 September 1998 Influence of floating gate tungsten polycide deposition technique on EEPROM electrical characteristics

Karine Ogier-Monnier, Philippe Boivin, Olivier Bonnaud

Proceedings Volume 3507, Process, Equipment, and Materials Control in Integrated Circuit Manufacturing IV; (1998) https://doi.org/10.1117/12.324339
Event: Microelectronic Manufacturing, 1998, Santa Clara, CA, United States

Abstract

In CMOS technology, polycide material is often used to from the gate electrode. This bilayer composed of tungsten silicide layer and of doped polycrystalline layer, preserves a good silicon/oxide interface and has low resistivity. Different processes can be used to deposit the polycide. The first process which is conventional corresponds to a polysilicon deposition in furnace followed by a POCl₃ doping technique. Then the tungsten silicide is deposited. The second process involved a single wafer reactor. It allows to deposit the in-situ doped polycrystalline layer an the WSi_x layer in the same equipment. The aim of this work is to study the impact of these tow processes on the electrical behavior of the EEPROM, more especially on the endurance and on data retention. After the presentation of the fabrication processes, physical and electrical characteristics of both types of devices are discussed. The conventional gate degrades more the cycling performance of the memory cell.

Citation Download Citation

Karine Ogier-Monnier, Philippe Boivin, and Olivier Bonnaud "Influence of floating gate tungsten polycide deposition technique on EEPROM electrical characteristics", Proc. SPIE 3507, Process, Equipment, and Materials Control in Integrated Circuit Manufacturing IV, (3 September 1998); https://doi.org/10.1117/12.324339

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