Ion projection lithography: November 2000 status and sub-70-nm prospects

Rainer Kaesmaier; Andreas Wolter; Hans Loeschner; Stefan Schunck

doi:10.1117/12.404858

20 October 2000 Ion projection lithography: November 2000 status and sub-70-nm prospects

Rainer Kaesmaier, Andreas Wolter, Hans Loeschner, Stefan Schunck

Proceedings Volume 4226, Microlithographic Techniques in Integrated Circuit Fabrication II; (2000) https://doi.org/10.1117/12.404858
Event: International Symposium on Microelectronics and Assembly, 2000, Singapore, Singapore

Abstract

Among all next generation lithography (NGL) options Ion Projection Lithography (IPL) offers the smallest (particle) wavelength of 5x10^{- 5}nm (l00keV Helium ions). Thus, 4x reduction ion-optics has diffraction limits <3nm even when using a numerical aperture as low as NAequals10^-5. As part of the European MEDEA IPL project headed by Infineon Technologies wide field ion-optics have been designed by IMS- Vienna with predicted resolution of 50nm within a 12.5mm exposure field. The ion-optics part of the PDT tool (PDT-IOS) has been realized and assembled. In parallel to the PDT-IOS effort, at Leica Jena a test bench for a vertical vacuum 300mm-wafer stage has been realized. Operation of magnetic bearing supported stage movement has already been demonstrated. As ASML vacuum compatible optical wafer alignment system, with 3nm(3(sigma) ) precision demonstrated in air, has been integrated to this wafer test bench system recently. Parallel to the IPL tool development, Infineon Technologies Mask House and the Institute for Microelectronics Stuttgart are intensively working on the development of IPL stencil masks with success in producing 150mm and 200mm stencil masks as reported elsewhere. This paper is focused on information about the status of the PDT-IOS tool.

Citation Download Citation

Rainer Kaesmaier, Andreas Wolter, Hans Loeschner, and Stefan Schunck "Ion projection lithography: November 2000 status and sub-70-nm prospects", Proc. SPIE 4226, Microlithographic Techniques in Integrated Circuit Fabrication II, (20 October 2000); https://doi.org/10.1117/12.404858

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available