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The application of Chromeless Phase Lithography, or 100% transmission attenuated PSM, has been used to demonstrate the potential for achieving quarter-wavelength optical lithography (0.2k1). As the demand to image sub-100nm features reaches to the semiconductor fabrication lines, the need for a robust lithography process capable of meeting high volume requirements is becoming more and more critical. The requirements for high-volume, low-k1 semiconductor manufacturing go beyond wafer imaging technology capable of the process latitude needed for lithography, but also includes data prep software that is capable of applying the details of the imaging technology to the design data, correcting for optical proximity effects, and outputting the necessary mask pattern data. It is also necessary to have a reticle manufacturing infrastructure capable of supporting large volume production with reliability and reasonable turn around time.
CPL technology has, by its nature, many elements that make it a strong candidate to meet mass production requirements for 65nm semiconductor technology products. Most important, CPL achieves the resolution enhancement by using a single reticle and does not require a second exposure with a trim mask. The CPL reticle is a variation of the attenuated phase shifting mask, and data preparation for the reticle manufacturing is very similar to what is needed for high-transmission attenuated PSM. It will be shown that as a result of the 100% transmission, the MEEF for CPL masks is very small and in some cases approaches zero. This allows for much larger CD tolerances for the reticle but results in significant limitations on correcting optical proximity effects by using CD bias alone. Methods for correcting through-pitch CD variations with the use of novel CPL pattern designs, bias, and scattering bars will be presented and correlated to wafer imaging results. These results will demonstrate the ability to control through-pitch CD's while maintaining the beneficial MEEF characteristics of CPL. Experimental results using a CPL reticle designed and manufactured for 65nm lithography exposed on an advanced 193nm ASML /1100 wafer scanner will be presented and discussed.
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