Assessing technology options for 65-nm logic circuits

Dipankar Pramanik; Michel L. Cote; Kevin Beaudette; Valery Axelrad

doi:10.1117/12.485256

10 July 2003 Assessing technology options for 65-nm logic circuits

Dipankar Pramanik, Michel L. Cote, Kevin Beaudette, Valery Axelrad

Proceedings Volume 5042, Design and Process Integration for Microelectronic Manufacturing; (2003) https://doi.org/10.1117/12.485256
Event: Advanced Microelectronic Manufacturing, 2003, Santa Clara, CA, United States

Abstract

The 2001 ITRS roadmap identified the need for tight coupling of design technology with manufacturing technology in order to ensure the successful production of circuits fabricated at the 65nm technology node. The design creation process for 65nm needs to efficiently explore the interaction between device, cell design and manufacturability. Using fast simulation tools for device and lithography simulation and an automated tool for standard cell generation, various process and cell architectural options were investigated. The average and standard deviation of line width had to be matched to the type of application because of the direct relationship between leakage current and performance. Best process latitude for poly line widths is achieved with Full Phase technology. It is shown that by matching design rules to the Full Phase capabilities and using automated layout tools, manufacturabilty could be optizmed without hurting density or performance.

Citation Download Citation

Dipankar Pramanik, Michel L. Cote, Kevin Beaudette, and Valery Axelrad "Assessing technology options for 65-nm logic circuits", Proc. SPIE 5042, Design and Process Integration for Microelectronic Manufacturing, (10 July 2003); https://doi.org/10.1117/12.485256

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