Inspection of integrated circuit databases through reticle and wafer simulation: an integrated approach to design for manufacturing (DFM)

William Howard; Jaione Tirapu Azpiroz; Yalin Xiong; Chris Mack; Gaurav Verma; William Volk; Harold Lehon; Yunfei Deng; Rui-fang Shi; James Culp; Scott Mansfield

doi:10.1117/12.604698

5 May 2005 Inspection of integrated circuit databases through reticle and wafer simulation: an integrated approach to design for manufacturing (DFM)

William Howard, Jaione Tirapu Azpiroz, Yalin Xiong, Chris Mack, Gaurav Verma, William Volk, Harold Lehon, Yunfei Deng, Rui-fang Shi, James Culp, Scott Mansfield

Author Affiliations +

Proceedings Volume 5756, Design and Process Integration for Microelectronic Manufacturing III; (2005) https://doi.org/10.1117/12.604698
Event: Microlithography 2005, 2005, San Jose, California, United States

Abstract

The present approach to Optical Proximity Correction (OPC) verification has evolved from a number of separate inspection strategies. OPC decoration is verified by a design rule or optical rule checker, the reticle is verified by a reticle inspection system, and the final wafers are verified by wafer inspection and metrology tools. Each verification step looks at a different representation of the desired device pattern with little or no data flowing between them. In this paper, we will report on a new inspection system called DesignScan that connects the data between the various abstraction layers. DesignScan inspects the OPC decorated design by simulating how the design will be transferred to the reticle layer and how that reticle will be imaged into resist across the full focus-exposure process window. The simulated images are compared to the desired pattern and defect detection algorithms are applied to determine if any unacceptable variations in the pattern occurs within the nominal process window. The end result is a new paradigm in design verification, moving beyond OPC verification at the design plane to process window verification at the wafer plane where it really matters. We will demonstrate the application of DesignScan to inspect full chip designs that utilized different Resolution Enhancement Technique (RET) and OPC methods. In doing so, we’ll demonstrate that DesignScan can identify the relative strengths and weaknesses of each methodology by highlighting areas of weak process window for each approach. We will present experimental wafer level results to verify the accuracy of the defect predictions.

Citation Download Citation

William Howard, Jaione Tirapu Azpiroz, Yalin Xiong, Chris Mack, Gaurav Verma, William Volk, Harold Lehon, Yunfei Deng, Rui-fang Shi, James Culp, and Scott Mansfield "Inspection of integrated circuit databases through reticle and wafer simulation: an integrated approach to design for manufacturing (DFM)", Proc. SPIE 5756, Design and Process Integration for Microelectronic Manufacturing III, (5 May 2005); https://doi.org/10.1117/12.604698

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