Model-based scattering bars implementation for 65nm and 45nm nodes using IML technology

Michael Hsu; Doug Van Den Broeke; Tom Laidig; Kurt E. Wampler; Uwe Hollerbach; Robert Socha; J. Fung Chen; Stephen Hsu; Xuelong Shi

doi:10.1117/12.617165

28 June 2005 Model-based scattering bars implementation for 65nm and 45nm nodes using IML technology

Michael Hsu, Doug Van Den Broeke, Tom Laidig, Kurt E. Wampler, Uwe Hollerbach, Robert Socha, J. Fung Chen, Stephen Hsu, Xuelong Shi

Author Affiliations +

Proceedings Volume 5853, Photomask and Next-Generation Lithography Mask Technology XII; (2005) https://doi.org/10.1117/12.617165
Event: Photomask and Next Generation Lithography Mask Technology XII, 2005, Yokohama, Japan

Abstract

Scattering Bars (SB) OPC, together with optimized illumination, is no doubt one of the critical enablers for low k₁ lithography manufacturing. The manufacturing implementation of SB so far has been mainly based on rule-based approach. While this has been working well, a more effective model-based approach is much more desired lithographically for manufacturing at 65nm and 45nm nodes. This is necessary to ensure sufficient process margin using hyper NA for patterning random IC design. In our model-based SB (M-SB) OPC implementation, we have based on the patented IML Technology from ASML MaskTools. In this report, we use both dark field contact hole and clear field poly gate mask to demonstrate this implementation methodology. It is also quite applicable for dark field trench masks, such as local interconnect mask with damascene metal. For our full-chip implementation flow, the first step is to determine the critical design area and then to proceed with NA and illumination optimization. We show that, using LithoCruiser, we are able to select the best NA in combination with optimum illumination via a Diffraction Optical Element (DOE). The decision to use a custom DOE or one from the available DOE library from ASML can be made based on predicted process performance and cost effectiveness. With optimized illumination, it is now possible to construct an interference map for the full-chip mask pattern. Utilizing the interference map, M-SB OPC is generated. Next, model OPC can be applied with the presence of M-SB for the entire chip. It is important to note here, that from our experience, the model OPC must be calibrated with the presence of SB in order to achieve the desired accuracy. We report the full-chip processing benchmark using MaskWeaver to apply both M-SB and model OPC. For actual patterning performance, we have verified the full chip OPC treatment using SLiC, a DFM tool from Cadence. This implementation methodology can be applied to binary chrome mask, attenuated PSM, and CPL.

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Michael Hsu, Doug Van Den Broeke, Tom Laidig, Kurt E. Wampler, Uwe Hollerbach, Robert Socha, J. Fung Chen, Stephen Hsu, and Xuelong Shi "Model-based scattering bars implementation for 65nm and 45nm nodes using IML technology", Proc. SPIE 5853, Photomask and Next-Generation Lithography Mask Technology XII, (28 June 2005); https://doi.org/10.1117/12.617165

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