Paper
20 March 2006 Enhancing DRAM printing process window by using inverse lithography technology (ILT)
Chih-Wei Chu, Becky Tsao, Karl Chiou, Snow Lee, Jerry Huang, Yong Liu, Timothy Lin, Andrew Moore, Linyong Pang
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Abstract
Inverse lithography technology (ILT) was studied during process development for four layers from memory semiconductor designs. This paper describes techniques used in each of the layers. So as to demonstrate this technology in a wide range of semiconductor patterns, we show results from all four layers. Polysilicon was chosen to demonstrate the selection of exposure/defocus (ED) points for constraining the inversion. Marking process window boundaries during a mask creation run was demonstrated on a contact hole layer. With a deep trench layer, mask constraints were varied and write times studied. Lastly, wafer SEM images were collected for an active layer to explore image fidelity though focus and CD stability along a line.
© (2006) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Chih-Wei Chu, Becky Tsao, Karl Chiou, Snow Lee, Jerry Huang, Yong Liu, Timothy Lin, Andrew Moore, and Linyong Pang "Enhancing DRAM printing process window by using inverse lithography technology (ILT)", Proc. SPIE 6154, Optical Microlithography XIX, 61543O (20 March 2006); https://doi.org/10.1117/12.657015
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Cited by 2 scholarly publications.
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KEYWORDS
Photomasks

Lithography

Image quality

Semiconductors

Semiconducting wafers

Printing

Light sources

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