Paper
20 May 2006 Etch analysis of patterns to comprehend manufacturability
Author Affiliations +
Abstract
Negative etch bias is often used to decrease the minimum linewidth beyond what is possible with lithography alone, for example 110 nm minimum CD in resist and 70 nm minimum CD after etch. If the minimum space that can be opened in resist is, for example, 30 nm a true 70 nm half-pitch can be achieved when an etch shrink is employed. Due to iso-dense bias and other proximity effects, however, positive etch bias can also occur. This leads to the unfavorable situation where litho must print lines in resist smaller than the lines in the final post-etch silicon. Due to positive etch bias, among other factors, it is possible to create a configuration that can be realized from the point of view of etch, but can not be created due to photolithography or mask constraints. Specific trouble spots include boundary regions which transition between one set of DRC rules and another. With a new highly accurate etch model, problematic configurations can be identified and used to modify the design to make the etch, photolithography, and mask construction processes realizable. This paper will demonstrate unrealizable pattern conditions that can be found using a non-linear etch model for OPC[R], leading to layout configuration changes which improve the mask construction and photolithography processes.
© (2006) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Daniel F. Beale and Lawrence S. Melvin III "Etch analysis of patterns to comprehend manufacturability", Proc. SPIE 6283, Photomask and Next-Generation Lithography Mask Technology XIII, 62832T (20 May 2006); https://doi.org/10.1117/12.681807
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Cited by 1 scholarly publication.
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KEYWORDS
Etching

Optical lithography

Process modeling

Manufacturing

Data modeling

Photoresist materials

Semiconducting wafers

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