Paper
20 August 1986 Mixing And Matching Of Wafer Steppers And Wafer Scanners For Cost-Effective, High-Volume Device Production
Harry Sewell, Myles Gansfried
Author Affiliations +
Abstract
The mixing and matching of Step-and-Repeat Alignment systems and wafer scanners is a viable method of providing the high levels of overlay accuracy and resolution that are now required in the manufacturing of the most advanced devices such as 1 MBIT DRAMs. At the same time, significant reduction of the production costs, especially on large wafers, are realized. The utilization of scanner systems allows very high wafer throughput, in excess of 100 wafers/hour. The utilization of Step-and-Repeat Alignment systems allows the reduction of overlay errors to less than 0.3 micron (98%). The mixing of equipment has been enhanced by the introduction of Universal Mix-and-Match Prealigners on the Micralign scanner systems. These prealigners are capable of simulating the performance of any Step-and-Repeat Alignment system prealigner by the use of wafer edge mapping techniques and special prealigner simulation algorithms in software. Using these prealigners, device arrays and alignment keys are accurately positioned on the wafers. This allows the implementation of automatic alignment systems and the maintenance of high wafer throughputs on the scanner systems. New developments in metrology equipment now allow the use of automated overlay measurement systems for the mapping of overlay errors on wafers. The extraction of equipment overlay correction factors is now possible. The implementation of such systems will allow ≤ 0.4-micron overlay processes, such as 1 MBIT DRAMs, to be run routinely on mixed equipment.
© (1986) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Harry Sewell and Myles Gansfried "Mixing And Matching Of Wafer Steppers And Wafer Scanners For Cost-Effective, High-Volume Device Production", Proc. SPIE 0633, Optical Microlithography V, (20 August 1986); https://doi.org/10.1117/12.963710
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KEYWORDS
Semiconducting wafers

Optical alignment

Scanners

Overlay metrology

Lithography

Distortion

Computer simulations

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