Paper
20 October 2006 Mask complexity reduction, quality assurance, and yield improvement through reduced layout variability
A. Balasinski, J. Cetin
Author Affiliations +
Abstract
Technology, CAD, and design are increasingly more challenged by Design-for-Manufacturability rules and guidelines required to improve pattern transfer quality to the reticle and silicon wafer. One key reason for this challenge is the variability of the layout, which for designs beyond the 100 nm technology node should no longer be subject only to short range design rule checks concerning individual layout features. To include the impact of medium and long-range pattern interactions (across-die or exposure field) into the design process, one should change layout architecture methodology distributed so far among multiple design groups and using manual drawing techniques or semi-automated tools with different quality standards. This task becomes even more important for the RF/analog layout where signal propagation is sensitive to device matching requirements and capacitive coupling. At that point, IC designer had two options to control the layout freedom: by enforcing new, more restrictive design rules or by using standardized, parameterized layout based on standard cells proven on silicon, including all electrically extracted RET, OPC, and dummy features. In this work, we will show that the standardized layout is the option preferred from the point of view of design, CAD, and technology.
© (2006) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
A. Balasinski and J. Cetin "Mask complexity reduction, quality assurance, and yield improvement through reduced layout variability", Proc. SPIE 6349, Photomask Technology 2006, 63490D (20 October 2006); https://doi.org/10.1117/12.685298
Advertisement
Advertisement
RIGHTS & PERMISSIONS
Get copyright permission  Get copyright permission on Copyright Marketplace
KEYWORDS
Computer aided design

Photomasks

Optical proximity correction

Manufacturing

Standards development

Field effect transistors

Design for manufacturing

RELATED CONTENT

DFM through correct process construction
Proceedings of SPIE (May 03 2004)
DfM requirements and ROI analysis for system-on-chip
Proceedings of SPIE (November 04 2005)
Integration of mask and silicon metrology in DFM
Proceedings of SPIE (March 12 2009)
Design, mask, and manufacturability
Proceedings of SPIE (December 06 2004)

Back to Top