Silicon-verified automatic DFM layout optimization: a calibration-lite model-based application to standard cells

Kuang-Kuo Lin; Ban P. Wong; Frank A. J. M. Driessen; Etsuya Morita; Simon Klaver

doi:10.1117/12.747021

30 October 2007 Silicon-verified automatic DFM layout optimization: a calibration-lite model-based application to standard cells

Kuang-Kuo Lin, Ban P. Wong, Frank A. J. M. Driessen, Etsuya Morita, Simon Klaver

Author Affiliations +

Proceedings Volume 6730, Photomask Technology 2007; 67300X (2007) https://doi.org/10.1117/12.747021
Event: SPIE Photomask Technology, 2007, Monterey, California, United States

Abstract

DFM considerations have become an indispensable and integral part of advanced nanometer semiconductor product designs. Traditional first-generation DFM tools have focused on functional lithography hotspot detections. While useful, these tools offer designers few hints on the complex layout fixings and the intricate trade-off decisions required. With these limitations, DFM layout optimization has become a tedious and inconsistent design endeavor. In addition, the long and intense calibration cycle required for the traditional DFM models have hindered their effectiveness and timeliness. An automatic DFM layout optimization system that performs systematic multi-objective functional and parametric DFM optimizations at early design phase will be introduced. A calibration-lite methodology that has expedited the DFM model set-ups will be discussed along with the silicon validation test pattern designs. Finally, both simulation and silicon experiment results will be presented.

Citation Download Citation

Kuang-Kuo Lin, Ban P. Wong, Frank A. J. M. Driessen, Etsuya Morita, and Simon Klaver "Silicon-verified automatic DFM layout optimization: a calibration-lite model-based application to standard cells", Proc. SPIE 6730, Photomask Technology 2007, 67300X (30 October 2007); https://doi.org/10.1117/12.747021

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