Paper
24 March 2008 Film stacking architecture for immersion lithography process
Author Affiliations +
Abstract
In immersion lithography process, film stacking architecture will be necessary due to film peeling. However, the architecture will restrict lithographic area within a wafer due to top side EBR accuracy In this paper, we report an effective film stacking architecture that also allows maximum lithographic area. This study used a new bevel rinse system on RF3 for all materials to make suitable film stacking on the top side bevel. This evaluation showed that the new bevel rinse system allows the maximum lithographic area and a clean wafer edge. Patterning defects were improved with suitable film stacking.
© (2008) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Tomohiro Goto, Masakazu Sanada, Tadashi Miyagi, Kazuhito Shigemori, Masashi Kanaoka, Shuichi Yasuda, Osamu Tamada, and Masaya Asai "Film stacking architecture for immersion lithography process", Proc. SPIE 6922, Metrology, Inspection, and Process Control for Microlithography XXII, 69222X (24 March 2008); https://doi.org/10.1117/12.772411
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Cited by 1 scholarly publication.
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KEYWORDS
Semiconducting wafers

Particles

Coating

Lithography

Diffractive optical elements

Immersion lithography

Inspection

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