Performance characteristics of a nanoscale double-gate reconfigurable array

Paul Beckett

doi:10.1117/12.814059

30 December 2008 Performance characteristics of a nanoscale double-gate reconfigurable array

Paul Beckett

Proceedings Volume 7268, Smart Structures, Devices, and Systems IV; 72680E (2008) https://doi.org/10.1117/12.814059
Event: SPIE Smart Materials, Nano- and Micro-Smart Systems, 2008, Melbourne, Australia

Abstract

The double gate transistor is a promising device applicable to deep sub-micron design due to its inherent resistance to short-channel effects and superior subthreshold performance. Using both TCAD and SPICE circuit simulation, it is shown that the characteristics of fully depleted dual-gate thin-body Schottky barrier silicon transistors will not only uncouple the conflicting requirements of high performance and low standby power in digital logic, but will also allow the development of a locally-connected reconfigurable computing mesh. The magnitude of the threshold shift effect will scale with device dimensions and will remain compatible with oxide reliability constraints. A field-programmable architecture based on the double gate transistor is described in which the operating point of the circuit is biased via one gate while the other gate is used to form the logic array, such that complex heterogeneous computing functions may be developed from this homogeneous, mesh-connected organization.

Citation Download Citation

Paul Beckett "Performance characteristics of a nanoscale double-gate reconfigurable array", Proc. SPIE 7268, Smart Structures, Devices, and Systems IV, 72680E (30 December 2008); https://doi.org/10.1117/12.814059

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