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As advanced manufacturing processes become more stable, the need to adapt new designs to fully utilize
the available manufacturing technology becomes a key technologic differentiator. However, many times
such gains can only be realized and evaluated during full chip analysis. It has been demonstrated that the
most accurate layout verification methods require application of the actual OPC recipes along with most of
the mask data preparation that defines the pattern transfer characteristics of the process. Still, this method in
many instances is not sufficiently fast to be used in a layout creation environment which undergoes
constant updates.
By doing an analysis of typical mask data processing, it is possible to determine that the most CPUintensive
computations are the OPC and contour simulation steps needed to perform layout printability
checks. Several researchers have tried to reduce the time it takes to compute the OPC mask by introducing
matrix convolutions of the layout with empirically calibrated two-dimensional functions. However,
most of these approaches do not provide a sufficient speed-up since they only replace the OPC computation
and still require a full contour computation. Another alternative is to try to find effective ways of pattern
matching those topologies that will exhibit transfer difficulties4, but such methods lack the ability to be
predictive beyond their calibration data.
In this paper we present a methodology that includes common resolution enhancement techniques, such as
retargeting and sub-resolution assist feature insertion, and which replaces the OPC computation and
subsequent contour calculation with an edge bias function based on an empirically-calibrated, directional,
two-dimensional function. Because the edge bias function does not provide adequate control over the
corner locations, a spline-based smoothing process is applied. The outcome is a piecewise-linear curve
similar to those obtained by full lithographic simulations.
Our results are analyzed from the point of view of runtime and matching with respect to a complete
verification process that uses full mask data preparation followed by production-quality contour
simulations under a variety of process variations, including perturbations to focus, mask bias and exposure.
One of the main concerns with using an empirical model is its ability to predict topologies that were not
part of the original calibration. While there is indeed a dependency on the model in regard to the data used
for calibration, the results indicate that this dependency is weak and that such models are able to provide
sufficient accuracy with much more tolerable computation times.
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