Lithography compliance check considering neighboring cell structures for robust cell design

Masahiro Miyairi; Shigeki Nojima; Shimon Maeda; Katsuyoshi Kodera; Ryuji Ogawa; Satoshi Tanaka

doi:10.1117/12.824278

11 May 2009 Lithography compliance check considering neighboring cell structures for robust cell design

Masahiro Miyairi, Shigeki Nojima, Shimon Maeda, Katsuyoshi Kodera, Ryuji Ogawa, Satoshi Tanaka

Proceedings Volume 7379, Photomask and Next-Generation Lithography Mask Technology XVI; 737911 (2009) https://doi.org/10.1117/12.824278
Event: Photomask and NGL Mask Technology XVI, 2009, Yokohama, Japan

Abstract

Lithography compliance check (LCC), which is verification of layouts using lithography simulation, is an essential step under the current low k1 lithography condition. In general, LCC starts from primitive cell block level and checks bigger block level in the final stage. However, hotspots may be found by chip level LCC although LCC does not find any hotspots in a primitive cell block check, because conventional LCC for primitive cell blocks cannot consider the influence of the optical proximity effect from neighboring cell structures at the chip level. This paper proposes a new verification method in order to resolve this issue. It consists of three steps. The first step is the same as the conventional method; run LCC and judge if there are hotspots, which need to be fixed. The second step is judge if there are warmspots, which represent the pattern structures with borderline litho margin, and if warmspots are found, add a pattern that makes process margin worst. The third step is to fix the hotspots changing from warmspots by adding the worst pattern. Based on this method, primitive cell block LCC can guarantee that there are no hotspots at the chip level without chip level LCC. We discuss the detail of process flow of this verification method and validate the effect of this method.

Citation Download Citation

Masahiro Miyairi, Shigeki Nojima, Shimon Maeda, Katsuyoshi Kodera, Ryuji Ogawa, and Satoshi Tanaka "Lithography compliance check considering neighboring cell structures for robust cell design", Proc. SPIE 7379, Photomask and Next-Generation Lithography Mask Technology XVI, 737911 (11 May 2009); https://doi.org/10.1117/12.824278

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KEYWORDS

Lithography

Logic

Optical proximity correction

Metals

Design for manufacturing

Manufacturing

Semiconducting wafers

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