Paper
30 March 2010 Accelerating the dual damascene process time by new filling material
Kung-Hsun Tsao, Yu-Huan Liu, Tsz-Yuan Chen, Chih-Jung Chen, C. C. Huang, Yung-Cheng Chang, Go Noya, Nick Hsiao, Simon Chiu, Vencent Chang, Tomohide Katayama, Hisashi Motobayashi
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Abstract
Dual damascene technique has been widely applied to IC device fabrication in copper interconnect process. For traditional via-first dual damascene application, a fill material is first employed to fill via to protect over-etching and punch-through of the bottom barrier layer during the trench-etch process. Etch-back process is then applied to remove excess overfill thickness and maintain a greater planar topography. To get better CD control, a thin organic BARC is finally coated to reduce reflectivity for trench patterning but not in this study. It is a multi-step and costly dual damascene process. In this study, a new gap-filling BARC material with good via fill and light absorption features was adopted to explore the via-first dual damascene process by skipping etch-back and BARC coating steps. The results show not only the reduction of process cycle time and cost saving but also the CP yield improvement based on data from pilot production of 0.11/0.13 μm logic device.
© (2010) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Kung-Hsun Tsao, Yu-Huan Liu, Tsz-Yuan Chen, Chih-Jung Chen, C. C. Huang, Yung-Cheng Chang, Go Noya, Nick Hsiao, Simon Chiu, Vencent Chang, Tomohide Katayama, and Hisashi Motobayashi "Accelerating the dual damascene process time by new filling material", Proc. SPIE 7639, Advances in Resist Materials and Processing Technology XXVII, 76392A (30 March 2010); https://doi.org/10.1117/12.855997
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KEYWORDS
Etching

Coating

Lithography

Optical lithography

Semiconducting wafers

Yield improvement

Absorption

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