Joint-optimization for SRAM and logic for 28nm node and below

Staf Verhaegen; Michael C. Smayling; Peter De Bisschop; Bart Laenens

doi:10.1117/12.846595

10 March 2010 Joint-optimization for SRAM and logic for 28nm node and below

Staf Verhaegen, Michael C. Smayling, Peter De Bisschop, Bart Laenens

Proceedings Volume 7641, Design for Manufacturability through Design-Process Integration IV; 764107 (2010) https://doi.org/10.1117/12.846595
Event: SPIE Advanced Lithography, 2010, San Jose, California, United States

Abstract

In current and next generation nodes lithography is pushed to low k1 lithography imaging regimes. A gridded design approach with lines and cuts has previously been shown to allow optimizing illuminator conditions for critical layers in logic designs.[1] The approach has shown good pattern fidelity and is expected to be scalable to the 7nm logic node. [2] A regular pattern for logic makes the optimization problem straightforward if only standard cells are used in a chip.[3,4] However, modern SOC's include large amounts of SRAM as well. The proposed approach truly optimizes both, instead of the conventional approach of sacrificing the SRAM because of logic layouts with bends and multiple pitches. The biggest problem in co-optimizing logic cells and SRAM bit cells is the orientation of critical layers. For SRAMs, the gate and metal1 layers have lines in parallel directions, while in standard cells they are perpendicular. This would require abandoning dipole illumination for the combined optimization, and at best using some form of quadrupole. The alternative is to design the logic and SRAMs to be unified from the beginning. In this case, critical layer orientations as well as pitches could be matched and each of the layers optimized for both functional sets of patterns. Choices of patterns can be made to achieve DSMO (Design-Source-Mask-Optimization). In the 28nm to 22nm logic nodes - with contacted pitches from 110nm to 90nm and metal1 pitches from 90nm to 70nm - one of the questions to answer is when and for which layers double patterning is needed. The limit of single patterning immersion lithography can only be explored through a smart combination of restricted designs and powerful sourcemask optimization tools. In this paper a 28nm SRAM block with bit and word line periphery will be used to look at choices for Design-Source-Mask-Optimization.

Citation Download Citation

Staf Verhaegen, Michael C. Smayling, Peter De Bisschop, and Bart Laenens "Joint-optimization for SRAM and logic for 28nm node and below", Proc. SPIE 7641, Design for Manufacturability through Design-Process Integration IV, 764107 (10 March 2010); https://doi.org/10.1117/12.846595

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available