Jet and flash imprint defectivity: assessment and reduction for semiconductor applications

Matt Malloy; Lloyd C. Litt; Steve Johnson; Douglas J. Resnick; David Lovell

doi:10.1117/12.881530

2 April 2011 Jet and flash imprint defectivity: assessment and reduction for semiconductor applications

Matt Malloy, Lloyd C. Litt, Steve Johnson, Douglas J. Resnick, David Lovell

Proceedings Volume 7970, Alternative Lithographic Technologies III; 797006 (2011) https://doi.org/10.1117/12.881530
Event: SPIE Advanced Lithography, 2011, San Jose, California, United States

Abstract

Defectivity has been historically identified as a leading technical roadblock to the implementation of nanoimprint lithography for semiconductor high volume manufacturing. The lack of confidence in nanoimprint's ability to meet defect requirements originates in part from the industry's past experiences with 1X lithography and the shortage in end-user generated defect data. SEMATECH has therefore initiated a defect assessment aimed at addressing these concerns. The goal is to determine whether nanoimprint, specifically Jet and Flash Imprint Lithography from Molecular Imprints, is capable of meeting semiconductor industry defect requirements. At this time, several cycles of learning have been completed in SEMATECH's defect assessment, with promising results. J-FIL process random defectivity of < 0.1 def/cm² has been demonstrated using a 120nm half-pitch template, providing proof of concept that a low defect nanoimprint process is possible. Template defectivity has also improved significantly as shown by a pre-production grade template at 80nm pitch. Cycles of learning continue on feature sizes down to 22nm.

Citation Download Citation

Matt Malloy, Lloyd C. Litt, Steve Johnson, Douglas J. Resnick, and David Lovell "Jet and flash imprint defectivity: assessment and reduction for semiconductor applications", Proc. SPIE 7970, Alternative Lithographic Technologies III, 797006 (2 April 2011); https://doi.org/10.1117/12.881530

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