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With the constant decrease of semiconductor device dimensions, gate Line Edge Roughness (LER) becomes one of the most important sources of device variability and needs to be controlled well below 2 nm for the future technological nodes of the semiconductor roadmap. Gate LER originates from photoresist (PR) LER that is partially transferred into the gate during the plasma etch process. A plasma treatment is typically used to reduce the PR LER before the transfer. We have shown that an HBr plasma treatment reduces the LER by about 30% whereas an HBr/O2 plasma treatment followed by a bake at 150°C can reduce the LER further, by about 50%. The LER control at the nanometer scale also requires accurate measurements. We have developed a technique for LER measurement based upon Atomic Force Microscopy (AFM). In this technique, the sample is tilted at about 45° and feature sidewalls are scanned along their length with the AFM tip to obtain three-dimensional images. The small radius of curvature of the tip together with the low noise level of a laboratory AFM result in high resolution images. Half profiles and LER values on all the height of the sidewalls are extracted from the 3D images using a procedure that we developed. The AFM technique is applied to the study of a full pattern transfer into a simplified gate stack starting from untreated PR, PR treated by a conventional HBr plasma, and PR treated by an HBr/O2 plasma followed by a bake at 150°C. It is found that plasma etching reduces the LER at each etching step. The reduction is much more important when starting from untreated PR which has the highest initial LER. However, the final LER in the Si layer remains significantly smaller when starting with cured PR, especially with PR cured by an HBr/O2 plasma treatment followed by a bake at 150°C.
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