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Historically IC (integrated circuit) device scaling has bridged the gap between technology nodes. Device size reduction
is enabled by increased pattern density, enhancing functionality and effectively reducing cost per chip. Exemplifying
this trend are aggressive reductions in memory cell sizes that have resulted in systems with diminishing area between
bit/word lines. This affords an even greater challenge in the patterning of contact level features that are inherently
difficult to resolve because of their relatively small area and complex aerial image. To accommodate these trends,
semiconductor device design has shifted toward the implementation of elliptical contact features. This empowers
designers to maximize the use of free device space, preserving contact area and effectively reducing the via dimension
just along a single axis. It is therefore critical to provide methods that enhance the resolving capacity of varying aspect
ratio vias for implementation in electronic design systems. Vortex masks, characterized by their helically induced
propagation of light and consequent dark core, afford great potential for the patterning of such features when coupled
with a high resolution negative tone resist system. This study investigates the integration of a vortex mask in a 193nm
immersion (193i) lithography system and qualifies its ability to augment aspect ratio through feature density using aerial
image vector simulation. It was found that vortex fabricated vias provide a distinct resolution advantage over
traditionally patterned contact features employing a 6% attenuated phase shift mask (APM). 1:1 features were
resolvable at 110nm pitch with a 38nm critical dimension (CD) and 110nm depth of focus (DOF) at 10% exposure
latitude (EL). Furthermore, iterative source-mask optimization was executed as means to augment aspect ratio. By
employing mask asymmetries and directionally biased sources aspect ratios ranging between 1:1 and 2:1 were
achievable, however, this range is ultimately dictated by pitch employed.
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