Effect of etch pattern transfer on local overlay (OVL) margin in 28nm gate integration.

Onintza Ros; Pascal Gouraud; Bertrand Le-Gratiet; Christian Gardin; Julien Ducoté; Erwine Pargon

doi:10.1117/12.2042080

28 March 2014 Effect of etch pattern transfer on local overlay (OVL) margin in 28nm gate integration.

Onintza Ros, Pascal Gouraud, Bertrand Le-Gratiet, Christian Gardin, Julien Ducoté, Erwine Pargon

Proceedings Volume 9054, Advanced Etch Technology for Nanopatterning III; 905406 (2014) https://doi.org/10.1117/12.2042080
Event: SPIE Advanced Lithography, 2014, San Jose, California, United States

Abstract

One of the main process control challenges in logic process integration is the contact to gate overlay. Usual ways for overlay control are run to run corrections (high order process corrections) and scanner control (baseliner control loop) to keep overlay within the very tight ITRS specifications, i.e. 7nm mean+3sigma. It is known that process integration can lead to specific overlay distortion (CMP, thermal treatment etc…) which are usually partly handled by high order process corrections at scanner level. In addition, recently we have shown that etch process can also lead to local overlay distortions, especially at the wafer edge [1]. In this paper we look into another overlay distortion level which can happen during etch processes. We will show that resist cure steps during gate patterning affect lithography defined profiles leading to local pattern shifting. This so called gate shifting has been characterized by etch process partitioning during a typical high-K metal gate patterning with spinon carbon and Si-ARC lithography stack onto a high-K metal gate / poly-silicon / oxide hard mask stack. We will show that modifying the resist-cure / Si-ARC open chemistry strongly contributes to gate shifting reduction by an equivalent of 40% overlay margin reduction.

Citation Download Citation

Onintza Ros, Pascal Gouraud, Bertrand Le-Gratiet, Christian Gardin, Julien Ducoté, and Erwine Pargon "Effect of etch pattern transfer on local overlay (OVL) margin in 28nm gate integration.", Proc. SPIE 9054, Advanced Etch Technology for Nanopatterning III, 905406 (28 March 2014); https://doi.org/10.1117/12.2042080

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available