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Starting from the 45nm technology node, systematic defectivity has a significant impact on device yield loss with each new technology node. The effort required to achieve patterning maturity with zero yield detractor is also significantly increasing with technology nodes. Within the manufacturing environment, new in-line wafer inspection methods have been developed to identify device systematic defects, including the process window qualification (PWQ) methodology used to characterize process robustness. Although patterning is characterized with PWQ methodology, some questions remain: How can we demonstrate that the measured process window is large enough to avoid design-based defects which will impact the device yield? Can we monitor the systematic yield loss on nominal wafers? From device test engineering point of view, systematic yield detractors are expected to be identified by Automated Test Pattern Generator (ATPG) test results diagnostics performed after electrical wafer sort (EWS). Test diagnostics can identify failed nets or cells causing systematic yield loss [1],[2]. Convergence from device failed nets and cells to failed manufacturing design pattern are usually based on assumptions that should be confirmed by an electrical failure analysis (EFA). However, many EFA investigations are required before the design pattern failures are found, and thus design pattern failure identification was costly in time and resources. With this situation, an opportunity to share knowledge exists between device test engineering and manufacturing environments to help with device yield improvement. This paper presents a new yield diagnostics flow dedicated to correlation of critical design patterns detected within manufacturing environment, with the observed device yield loss. The results obtained with this new flow on a 28nm technology device are described, with the defects of interest and the device yield impact for each design pattern. The EFA done to validate the design pattern to yield correlation are also presented, including physical cross sections. Finally, the application of this new flow for systematic design pattern yield monitoring, compared to classic inline wafer inspection methods, is discussed.
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