Intra-lot wafer by wafer overlay control using integrated and standalone metrology combined sampling

Young Sin Choi; Young Sun Nam; Dong Han Lee; Jae Il Lee; Young Seog Kang; Se Yeon Jang; Jeong Heung Kong

doi:10.1117/12.2219922

15 March 2016 Intra-lot wafer by wafer overlay control using integrated and standalone metrology combined sampling

Young Sin Choi, Young Sun Nam, Dong Han Lee, Jae Il Lee, Young Seog Kang, Se Yeon Jang, Jeong Heung Kong

Proceedings Volume 9780, Optical Microlithography XXIX; 978009 (2016) https://doi.org/10.1117/12.2219922
Event: SPIE Advanced Lithography, 2016, San Jose, California, United States

Abstract

As overlay margin is getting tighter, traditional overlay correction method is not enough to secure more overlay margin without extended correction potential on lithography tool. Timely, the lithography tool has a capability of wafer to wafer correction. From these well-timed industry’s preparations, the uncorrected overlay error from current sampling in a lot could be corrected for yield enhancement.

In this paper, overlay budget break was performed prior to experiments with the purpose of estimating amount of overlay improvement. And wafer to wafer correction was simulated to the specified layer of a 2x node DRAM device. As a result, not only maximum 94.4% of residual variation improvement is estimated, but also recognized that more samplings to cover all wafer’s behavior is inevitable. Integrated metrology with optimized sampling scheme was also introduced as a supportive method for more samplings.

Citation Download Citation

Young Sin Choi, Young Sun Nam, Dong Han Lee, Jae Il Lee, Young Seog Kang, Se Yeon Jang, and Jeong Heung Kong "Intra-lot wafer by wafer overlay control using integrated and standalone metrology combined sampling", Proc. SPIE 9780, Optical Microlithography XXIX, 978009 (15 March 2016); https://doi.org/10.1117/12.2219922

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