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In this manuscript, this conventional issue will be demonstrated which is either over exposure in logic area or under exposure in bitcell area. The selective rule-based re-targeting concerning active layer will also be discussed, together with the improved wafer CDSEM data. The alternative method is to achieve different mean-to-nominal in different reticle areas which can be realized by lithography tolerance MPC during reticle process. The investigation of alternative methods will be presented, as well as the trade-off between them to improve the wafer uniformity and process margin of implant layers.
We have investigated three manufacturing sites for a 28nm first-metal layer reticle. Two of them were manufactured with a comparable process using the same advanced reticle binary blank material. For the third site a different reticle blank material with a relatively thin absorber layer thickness was used which was made with a comparable reticle process. The optical proximity correction (OPC) test patterns were designed with two different dummy patterns. The CD differences of the three reticles will be demonstrated for different dummy pattern and will be discussed individually. All three reticles have been exposed and the respective wafer critical dimension through pitch (CDTP) and linearity performance is demonstrated. Also the line-end performance for two dimensional (2D) structures is shown for the three sites of the reticle. The wafer CD difference for CDTP, linearity, and 2D structures are also discussed.
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