Ms. Maxime Gatefait Profile

Maxime Gatefait

at STMicroelectronics

SPIE Involvement:

Author

Publications (19)

Proceedings Article | 27 April 2023 Poster + Paper

Optimizations of APC multivariate algorithm for linear mix and match overlay control

Benjamin Duclaux, Maxime Gatefait, Alice Pelletier, Laurent Lecarpentier, Pierre Leveque, Cédric Monget

Proceedings Volume 12496, 1249627 (2023) https://doi.org/10.1117/12.2655762

KEYWORDS: Scanners, Advanced process control, Mathematical optimization, Overlay metrology, Feedback loops, Process modeling, Lithography

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Proceedings Article | 20 March 2020 Presentation + Paper

Run to run and model variability of overlay high order process corrections for mean intrafield signatures

Benjamin Duclaux, Maxime Gatefait, Olivier Mermet, Jean-Damien Chapon

Proceedings Volume 11325, 113251K (2020) https://doi.org/10.1117/12.2551062

KEYWORDS: Semiconducting wafers, Overlay metrology, Reticles, Scanners, Metrology, Data modeling, Sensors, Data corrections, Process modeling, Performance modeling, Lithographic process control

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Proceedings Article | 20 March 2020 Paper

Mitigating gain, effort and cost for EOW overlay control

Olivier Mermet, Maxime Gatefait, Didier Dabernat, Florent Dettoni, Benjamin Duclaux, Bertrand Le-Gratiet

Proceedings Volume 11325, 113251W (2020) https://doi.org/10.1117/12.2548308

KEYWORDS: Etching, Semiconducting wafers, Scanners, Overlay metrology, Contamination, Lithography, Plasma

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Proceedings Article | 13 March 2018 Presentation + Paper

Approaches of multilayer overlay process control for 28nm FD-SOI derivative applications

Benjamin Duclaux, Jean De Caunes, Robin Perrier, Maxime Gatefait, Bertrand Le Gratiet, Jean-Damien Chapon, Cédric Monget

Proceedings Volume 10585, 105851C (2018) https://doi.org/10.1117/12.2292446

KEYWORDS: Overlay metrology, Optical alignment, Scanners, Process control, Data modeling, Reticles, Reliability, Optical lithography

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Proceedings Article | 24 March 2016 Paper

An evaluation of edge roll off on 28nm FDSOI (fully depleted silicon on insulator) product

M. Gatefait, B. Le-Gratiet, C. Prentice, T. Hasan

Proceedings Volume 9778, 97782Y (2016) https://doi.org/10.1117/12.2218859

KEYWORDS: Scanners, Metrology, Image processing, Process control, Silicon, Sensors, Overlay metrology, Inspection, Forward error correction, Electroluminescence, Visualization, Diffraction, Field emission displays

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Proceedings Article | 23 October 2015 Paper

Higher order feed-forward control of reticle writing error fingerprints

Richard van Haren, Hakki Ergun Cekli, Jan Beltman, Anne Pastol, Frank Sundermann, Maxime Gatefait

Proceedings Volume 9635, 963507 (2015) https://doi.org/10.1117/12.2197556

KEYWORDS: Metrology, Reticles, Photomasks, Overlay metrology, Scanners, Image registration, Semiconducting wafers, Optical alignment, Data modeling, Pellicles

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The understanding and control of the intra-field overlay budget becomes crucial particularly after the introduction of multi-patterning applications. The intra-field overlay budget is built-up out of many contributors, each with its own characteristic. Some of them are (semi-)static like the reticle writing error (RWE) fingerprint, the scanner lens fingerprint, or the intra-field processing signature. Others are more dynamic. Examples are reticle heating and lens heating due to the absorption of a small portion of the exposure light. Ideally, all overlay contributors that are understood and known could be taken out of the feed-back control loop and send as feed-forward corrections to the scanner. As a consequence, only non-correctable overlay residuals are measured on the wafer.

In the current work, we have studied the possibility to characterize the reticle writing error fingerprint by an off-line position measurement tool and use this information to send feed-forward corrections to the ASML TWINSCAN^TM exposure tool. The current work is an extension of the work we published earlier. To this end, we have selected a reticle pair out of 50 production reticles that are used to manufacture a 28-nm technology device. These two reticles are special in the sense that the delta fingerprint contains a significant higher order RWE signature. While previously only the linear parameters were sent as feed-forward corrections to the ASML TWINSCAN^TM exposure tool, this time we additionally demonstrate the capability to correct for the non-linear terms as well. Since the concept heavily relies on the quality of the off-line mask registration measurements, a state-of-the-art reticle registration tool was chosen. Special care was taken to eliminate any effects of the tool induced shifts that may affect the quality of the measurements. The on-wafer overlay verification measurements were performed on an ASML YieldStar metrology tool as well as on a different vendor tool.

In conclusion, we have extended and proven the concept of using off-line reticle registration measurements to enable higher order feed-forward corrections the ASML TWINSCAN^TM scanner. This capability has been verified by on-wafer overlay measurements. It is demonstrated that the RWE contribution in the overlay budget can be taken out of the feedback control loop and sent as feed-forward corrections instead. This concept can easily be extended when more scanner corrections become available.

Proceedings Article | 4 September 2015 Paper

AGILE integration into APC for high mix logic fab

M. Gatefait, A. Lam, B. Le Gratiet, M. Mikolajczak, V. Morin, N. Chojnowski, Z. Kocsis, I. Smith, J. Decaunes, A. Ostrovsky, C. Monget

Proceedings Volume 9661, 96610P (2015) https://doi.org/10.1117/12.2194746

KEYWORDS: Sensors, Metrology, Semiconducting wafers, Logic, Data processing, Metals, Wafer-level optics, Optical properties, Photomasks, Scanners

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For C040 technology and below, photolithographic depth of focus control and dispersion improvement is essential to secure product functionality. Critical 193nm immersion layers present initial focus process windows close to machine control capability. For previous technologies, the standard scanner sensor (Level sensor - LS) was used to map wafer topology and expose the wafer at the right Focus. Such optical embedded metrology, based on light reflection, suffers from reading issues that cannot be neglected anymore. Metrology errors are correlated to inspected product area for which material types and densities change, and so optical properties are not constant. Various optical phenomena occur across the product field during wafer inspection and have an effect on the quality and position of the reflected light. This can result in incorrect heights being recorded and exposures possibly being done out of focus. Focus inaccuracy associated to aggressive process windows on critical layers will directly impact product realization and therefore functionality and yield. ASML has introduced an air gauge sensor to complement the optical level sensor and lead to optimal topology metrology. The use of this new sensor is managed by the AGILE (Air Gauge Improved process LEveling) application. This measurement with no optical dependency will correct for optical inaccuracy of level sensor, and so improve best focus dispersion across the product. Due to the fact that stack complexity is more and more important through process steps flow, optical perturbation of standard Level sensor metrology is increasing and is becoming maximum for metallization layers. For these reasons AGILE feature implementation was first considered for contact and all metal layers. Another key point is that standard metrology will be sensitive to layer and reticle/product density. The gain of Agile will be enhanced for multiple product contribution mask and for complex System on Chip. Into ST context (High mix logic Fab) in term of product and technology portfolio AGILE corrects for up to 120nm of product topography error on process layer with less than 50nm depth of focus Based on tool functionalities delivered by ASML and on high volume manufacturing requirement, AGILE integration is a real challenge. Regarding ST requirements “Automatic AGILE” functionality developed by ASML was not a turnkey solution and a dedicated functionality was needed. A “ST homemade AGILE integration” has been fully developed and implemented within ASML and ST constraints. This paper describes this integration in our Advanced Process Control platform (APC).

SPIE Journal Paper | 10 April 2015

Patterning critical dimension control for advanced logic nodes

Bertrand Le-Gratiet, Jean De-Caunes, Maxime Gatefait, Auguste Lam, Alain Ostrovsky, Jonathan Planchot, Vincent Farys, Julien Ducoté, Marc Mikolajczak, Vincent Morin, Nicolas Chojnowski, Frank Sundermann, Alice Pelletier, Regis Bouyssou, Cedric Monget, Jean-Damien Chapon, Bastien Orlando, Laurene Babaud, Céline Lapeyre, Emek Yesilada, Anna Szucs, Jean-Christophe Michel, Latifa Desvoivres, Onintza Ros Bengoechea, Pascal Gouraud

JM3, Vol. 14, Issue 02, 021103, (April 2015) https://doi.org/10.1117/12.10.1117/1.JMM.14.2.021103

KEYWORDS: Semiconducting wafers, Optical lithography, Critical dimension metrology, Process control, Photomasks, Etching, Logic, Metrology, Lithography, Optical proximity correction

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Proceedings Article | 19 March 2015 Paper

Pattern recognition and data mining techniques to identify factors in wafer processing and control determining overlay error

Auguste Lam, Alexander Ypma, Maxime Gatefait, David Deckers, Arne Koopman, Richard van Haren, Jan Beltman

Proceedings Volume 9424, 94241L (2015) https://doi.org/10.1117/12.2085497

KEYWORDS: Semiconducting wafers, Overlay metrology, Reticles, Optical alignment, Data mining, Pattern recognition, Scanners, Data modeling, Databases, Metrology

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Proceedings Article | 29 October 2014 Paper

Impact of reticle writing errors on the on-product overlay performance

Richard van Haren, Hakki Ergun Cekli, Xing Lan Liu, Jan Beltman, Anne Pastol, Jean Massin, Emilie Dupre La Tour, Maxime Gatefait, Frank Sundermann

Proceedings Volume 9235, 923522 (2014) https://doi.org/10.1117/12.2069315

KEYWORDS: Reticles, Semiconducting wafers, Scanners, Photomasks, Overlay metrology, Optical alignment, Metals, Image registration, Etching, Metrology

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The on-product overlay specification and Advanced Process Control (APC) are getting extremely challenging particularly after the introduction of multi-patterning applications like Litho-Etch-Litho-Etch (LELE). While the Reticle Writing Error (RWE) contribution could be marginalized for quite some time in the layer-to-layer overlay budget, it will become one of the dominating overlay contributors when the intra-layer overlay budget is considered. While most of the overlay contributors like wafer processing, scanner status, reticle transmission, dose, illumination conditions drop out of the intra-layer overlay budget, this is certainly not the case for reticle to reticle writing differences. In this work, we have studied the impact of the RWE on the on-product overlay performance. We show that the RWE can be characterized by an off-line mask registration tool and the modelled results can be sent as feed-forward corrections to the ASML TWINSCAN^TM. By doing so, the overlay control complexity (e.g. send-ahead wafers, APC settling time) can be reduced significantly. Off-line characterization enables that all reticles virtually become equal after correction (at least to the level of correction capability of the scanner). This means that all higher order RWE contributions (currently up to a third order polynomial) can be removed from the fingerprint. We show that out of 50 production reticles (FEOL, 28-nm technology), 30% can be improved on residual level when non-linear feed-forward corrections are considered as well. The additional benefit of feeding forward linear corrections to the scanner is even higher: it is anticipated that a large portion of the APC variation might find its origin in the RWE contribution. In order to send feed-forward corrections to the scanner, we obviously rely on the quality of the off-line RWE measurements. These measurements are usually provided by a registration tool at the mask shop. To secure the quality, an independent experimental verification test was developed to check if off-line RWE measurements can be used as feed-forward corrections to the scanner. The test has been executed on an ASML NXT: 1950i scanner and was designed such to isolate the reticle writing error contribution. The match between the off-line measurements and the experiment is striking.

Proceedings Article | 17 October 2014 Paper

How holistic process control translates into high mix logic fab APC?

B. Le-Gratiet, M. Gatefait, J. Ducotè, J. Decaunes, A. Lam, B. Beraud, M. Mikolajczak, A. Pelletier, B. Orlando, F. Sundermann, A. Ostrovsky, C. Lapeyre

Proceedings Volume 9231, 92310V (2014) https://doi.org/10.1117/12.2064795

KEYWORDS: Semiconducting wafers, Photomasks, Process control, Scanners, Metrology, Etching, Databases, Logic, Data modeling, Control systems

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Proceedings Article | 10 April 2013 Paper

Overlay improvement through lot-based feed-forward: applications to various 28nm node lithography operations

B. Orlando, M. Gatefait, J. De-Caunes, P.J. Goirand

Proceedings Volume 8681, 868117 (2013) https://doi.org/10.1117/12.2011117

KEYWORDS: Lithography, Overlay metrology, 193nm lithography, Semiconducting wafers, Double patterning technology, Optical alignment, Optical lithography, Scanners, Remote sensing, Control systems

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Proceedings Article | 10 April 2013 Paper

Scatterometry-based dose and focus decorrelation: applications to 28nm contact holes patterning intrafield focus investigations

B. Orlando, N. Spaziani, N. Socquet, R. Bouyssou, M. Gatefait, P.J. Goirand

Proceedings Volume 8681, 868118 (2013) https://doi.org/10.1117/12.2011122

KEYWORDS: 3D modeling, Scatterometry, Optical lithography, Critical dimension metrology, Scatter measurement, Lithography, Semiconducting wafers, Process control, Silicon, Silicon carbide

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Proceedings Article | 10 April 2013 Paper

Toward 7nm target on product overlay for C028 FDSOI technology

Maxime Gatefait, Bertrand Le-Gratiet, Pierre Jerome Goirand, Auguste Lam, Richard Van Haren, Anne Pastol, Maya Doytcheva, Xing Lan Liu, Jan Beltman

Proceedings Volume 8681, 868105 (2013) https://doi.org/10.1117/12.2011099

KEYWORDS: Semiconducting wafers, Overlay metrology, Reticles, Etching, Contamination, Metrology, Scanners, Lithography, Data modeling, Distortion

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Proceedings Article | 2 April 2010 Paper

Overlay breakdown methodology on immersion scanner

Auguste Lam, Francois Pasqualini, Jean de Caunes, Maxime Gatefait

Proceedings Volume 7638, 76383L (2010) https://doi.org/10.1117/12.849245

KEYWORDS: Semiconducting wafers, Overlay metrology, Scanners, Data mining, Optical alignment, Metrology, Reticles, Distance measurement, Data modeling, Process modeling

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Proceedings Article | 24 March 2009 Paper

Comparison of physical gate-CD with in-die at-speed non-contact measurements for bin-yield and process optimization

J. Vickers, J. Galvier, W. Doedel, G. Steinbrueck, B. Borot, M. Gatefait, P. Gouraud, P. Gros, G. Johnson, M. Babazadeh, M. Pelella, N. Pakdaman

Proceedings Volume 7272, 72724C (2009) https://doi.org/10.1117/12.823822

KEYWORDS: Semiconducting wafers, Critical dimension metrology, Metrology, Optical lithography, Signal detection, Process control, Manufacturing, Oscillators, Reticles, Control systems

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Proceedings Article | 22 March 2008 Paper

Process control for 45 nm CMOS logic gate patterning

Bertrand Le Gratiet, Pascal Gouraud, Enrique Aparicio, Laurene Babaud, Karen Dabertrand, Mathieu Touchet, Stephanie Kremer, Catherine Chaton, Franck Foussadier, Frank Sundermann, Jean Massin, Jean-Damien Chapon, Maxime Gatefait, Blandine Minghetti, Jean de-Caunes, Daniel Boutin

Proceedings Volume 6922, 69220Z (2008) https://doi.org/10.1117/12.776889

KEYWORDS: Semiconducting wafers, Etching, Critical dimension metrology, Optical lithography, Scatterometry, Reticles, Scanners, Photomasks, Process control, Immersion lithography

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Proceedings Article | 22 March 2008 Paper

Industrial characterization of scatterometry for advanced APC of 65 nm CMOS logic gate patterning

Karen Dabertrand, Mathieu Touchet, Stephanie Kremer, Catherine Chaton, Maxime Gatefait, Enrique Aparicio, Marco Polli, Jean-Claude Royer

Proceedings Volume 6922, 69220W (2008) https://doi.org/10.1117/12.771614

KEYWORDS: Critical dimension metrology, Scatterometry, Optical lithography, Scanning electron microscopy, Etching, Single crystal X-ray diffraction, Semiconducting wafers, Diffractive optical elements, Carbon, Scatter measurement

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Proceedings Article | 7 March 2008 Paper

Improving lithography intra wafer CD for C045 implant layers using STI thickness feed forward?

Jean Massin, Bastien Orlando, Maxime Gatefait, Jean-Damien Chapon, Bertrand Le-Gratiet, Blandine Minghetti, Pierre-Jérôme Goirand

Proceedings Volume 6924, 69244M (2008) https://doi.org/10.1117/12.775708

KEYWORDS: Oxides, Critical dimension metrology, Metrology, Chemical mechanical planarization, Logic, Semiconducting wafers, Etching, Optical lithography, Lithography, Scanners

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Showing 5 of 19 publications

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