Dr. Vivek K. Singh Profile

Dr. Vivek K. Singh

Vice President at NVIDIA

SPIE Involvement:

Conference Program Committee | Author

Proceedings Article | 30 April 2023 Open Access

Accelerated computing for silicon leadership

Vivek Singh

Proceedings Volume 12495, 1249502 (2023) https://doi.org/10.1117/12.2669884

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Proceedings Article | 28 April 2023 Presentation + Paper

Frequency-informed deep-learning denoising method supporting sub-nm metrology for high NA EUV lithography

Minjung Kim, Dorin Cerbu, Selim Dogru, Kumara Sastry, Gian Lorusso, Mohamed Zidan, Mohamed Saib, Joren Severi, Danilo De Simone, Vivek Singh

Proceedings Volume 12495, 124951D (2023) https://doi.org/10.1117/12.2661138

KEYWORDS: Extreme ultraviolet lithography, Photoresist technology, Line edge roughness, Critical dimension metrology, Critical dimension scanning electron microscopy, Image processing, Signal to noise ratio, Denoising, Scanning electron microscopy, Metrology, Line width roughness, Artificial intelligence, Machine learning

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Proceedings Article | 13 June 2022 Presentation

Computational lithography: accelerating the future

Vivek Singh

Proceedings Volume 12052, 1205207 (2022) https://doi.org/10.1117/12.2640423

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Proceedings Article | 15 March 2012 Paper

Mesoscale simulation of the line-edge structure during positive and negative tone resist development process

Hiroshi Morita, Ichiro Okabe, Saurabh Agarwal, Vivek Singh

Proceedings Volume 8325, 83250J (2012) https://doi.org/10.1117/12.916389

KEYWORDS: Polymers, Line edge roughness, Particles, Photoresist materials, Photoresist processing, Calibration, Photoresist developing, Polymer thin films, Molecules, Lithography

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Proceedings Article | 3 April 2010 Paper

The role of strong phase shift masks in Intel's DFM infrastructure development

Richard Schenker, Vivek Singh, Yan Borodovsky

Proceedings Volume 7641, 76410S (2010) https://doi.org/10.1117/12.849022

KEYWORDS: Photomasks, Optical lithography, Glasses, Design for manufacturing, Phase shifts, SRAF, Semiconducting wafers, Cadmium, Metals, Lithography

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Proceedings Article | 7 March 2008 Paper

Integration of pixelated phase masks for full-chip random logic layers

Richard Schenker, Srinivas Bollepalli, Bin Hu, Kenny Toh, Vivek Singh, Karmen Yung, Wen-hao Cheng, Yan Borodovsky

Proceedings Volume 6924, 69240I (2008) https://doi.org/10.1117/12.771677

KEYWORDS: Photomasks, Optical lithography, Glasses, Semiconducting wafers, SRAF, Cadmium, Phase shifts, Modulation, Image transmission, Etching

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Proceedings Article | 7 March 2008 Paper

Making a trillion pixels dance

Vivek Singh, Bin Hu, Kenny Toh, Srinivas Bollepalli, Stephan Wagner, Yan Borodovsky

Proceedings Volume 6924, 69240S (2008) https://doi.org/10.1117/12.773248

KEYWORDS: Photomasks, Optical proximity correction, Manufacturing, Image quality, Glasses, Lithography, Optical lithography, Computational lithography, Optimization (mathematics), Semiconducting wafers

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In June 2007, Intel announced a new pixelated mask technology. This technology was created to address the problem caused by the growing gap between the lithography wavelength and the feature sizes patterned with it. As this gap has increased, the quality of the image has deteriorated. About a decade ago, Optical Proximity Correction (OPC) was introduced to bridge this gap, but as this gap continued to increase, one could not rely on the same basic set of techniques to maintain image quality. The computational lithography group at Intel sought to alleviate this problem by experimenting with additional degrees of freedom within the mask. This paper describes the resulting pixelated mask technology, and some of the computational methods used to create it. The first key element of this technology is a thick mask model. We realized very early in the development that, unlike traditional OPC methods, the pixelated mask would require a very accurate thick mask model. Whereas in the traditional methods, one can use the relatively coarse approximations such as the boundary layer method, use of such techniques resulted not just in incorrect sizing of parts of the pattern, but in whole features missing. We built on top of previously published domain decomposition methods, and incorporated limitations of the mask manufacturing process, to create an accurate thick mask model. Several additional computational techniques were invoked to substantially increase the speed of this method to a point that it was feasible for full chip tapeout. A second key element of the computational scheme was the comprehension of mask manufacturability, including the vital issue of the number of colors in the mask. While it is obvious that use of three or more colors will give the best image, one has to be practical about projecting mask manufacturing capabilities for such a complex mask. To circumvent this serious issue, we eventually settled on a two color mask - comprising plain glass and etched glass. In addition, there were several smaller manufacturability concerns, for example a "1X1" glass pillar (an isolated 0 phase pixel) were susceptible to collapse under the stress of mask processing, and therefore these had to be constrained out of the final configuration. A third key element was defining the objective function. We experimented with a large number of choices and eventually settled on a form that allows us to trade-off fidelity and contrast. A fourth key element was the optimization algorithm. The number of possible configurations for a trillion pixels present on our final product mask is greater than the number of total elementary particles in the known universe, so finding the proverbial needle in this haystack was difficult to say the least. We chose a mixture of stochastic and direct descent algorithms to find an arrangement that meets the demands. While we have not proved we are close to the absolute global minimum, we conducted several experiments to suggest this is the case. A fifth key element, and a large one at that, was scaling up our software system from micron length scale to centimeter length scale required for full chip tapeout. This software, in turn, has several key components - hierarchy handling, the non-trivial handling of pixelated domain boundaries, repair of regions not converged in terms of image quality, and verification of the entire assembled database. All elements described above were validated through the tapeout of an actual mask to pattern the most complex metal layer for the leading 65nm node microprocessor in high volume manufacturing. This very first experimental tapeout resulted in wafer parts yield comparable to yields on mass produced wafers made with production 65nm technology.

Proceedings Article | 7 March 2008 Paper

Pixelated phase mask as novel lithography RET

Yan Borodovsky, Wen-Hao Cheng, Richard Schenker, Vivek Singh

Proceedings Volume 6924, 69240E (2008) https://doi.org/10.1117/12.772116

KEYWORDS: Photomasks, Glasses, Optical lithography, Mask making, Near field, Semiconducting wafers, Resolution enhancement technologies, Imaging systems, Projection systems, Image transmission

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Proceedings Article | 24 January 2008 Paper

Computational lithography: the new enabler of Moore's Law

Vivek Singh

Proceedings Volume 6827, 68271Q (2008) https://doi.org/10.1117/12.780063

KEYWORDS: Photomasks, Tin, Image quality, Computational lithography, Lithography, Optical proximity correction, Transistors, Manufacturing, Bridges, Optical lithography

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Proceedings Article | 29 March 2006 Paper

Defect marginality screen for resists patterned in random bright-field layout

David Fryer, Vivek Singh, Andrew Muray, Sushil Dhoot, Sam Sivakumar

Proceedings Volume 6153, 61530U (2006) https://doi.org/10.1117/12.658060

KEYWORDS: Stereolithography, Lithography, Optical lithography, Photomasks, FT-IR spectroscopy, Data modeling, Resolution enhancement technologies, Reticles, Model-based design, Photoresist materials

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Proceedings Article | 14 May 2004 Paper

Proximity correction and k1 performance for resists with nonoptical patterning response

David Fryer, Vivek Singh, Thanh Phung, Peng Liu

Proceedings Volume 5376, (2004) https://doi.org/10.1117/12.537701

KEYWORDS: Data modeling, Optical lithography, Photomasks, Interfaces, Systems modeling, Scanning electron microscopy, Oxides, Thermal effects, Optical proximity correction, Lithography

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Proceedings Article | 16 June 2003 Paper

Implementing flare compensation for EUV masks through localized mask CD resizing

Christof Krautschik, Manish Chandhok, Guojing Zhang, Sang Hun Lee, Michael Goldstein, Eric Panning, Bryan Rice, Robert Bristol, Vivek Singh

Proceedings Volume 5037, (2003) https://doi.org/10.1117/12.482344

KEYWORDS: Photomasks, Critical dimension metrology, Point spread functions, Chromium, Cadmium, Optical proximity correction, Extreme ultraviolet, Extreme ultraviolet lithography, Convolution, Mirrors

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SPIE Journal Paper | 1 October 2002

Relevance of technology computer aided design (TCAD) to process-aware design

Vivek Singh, Jorge Garcia-Colevatti

JM3, Vol. 1, Issue 03, (October 2002) https://doi.org/10.1117/12.10.1117/1.1508411

KEYWORDS: Computer aided design, TCAD, Optical proximity correction, Lithography, Solid modeling, Integrated circuits, Integrated circuit design, Product engineering, Performance modeling, Photoresist materials

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Proceedings Article | 1 August 2002 Paper

Lithography strategy for 65-nm node

Yan Borodovsky, Richard Schenker, Gary Allen, Edita Tejnil, David Hwang, Fu-Chang Lo, Vivek Singh, Robert Gleason, Joseph Brandenburg, Robert Bigwood

Proceedings Volume 4754, (2002) https://doi.org/10.1117/12.476916

KEYWORDS: Optical lithography, Photomasks, Optical proximity correction, Manufacturing, Inspection, Lithography, 193nm lithography, Phase shifts, Mask making, Semiconducting wafers

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Proceedings Article | 12 July 2002 Paper

Relevance of TCAD to process-aware design

Vivek Singh, Jorge Garcia-Colevatti

Proceedings Volume 4692, (2002) https://doi.org/10.1117/12.475675

KEYWORDS: TCAD, Optical proximity correction, Computer aided design, Lithography, Data modeling, Calibration, Manufacturing, Integrated circuit design, Device simulation, Monte Carlo methods

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Proceedings Article | 24 August 2001 Paper

Understanding molecular-level effects during post-exposure processing

Gerard Schmid, Mark Smith, Chris Mack, Vivek Singh, Sean Burns, C. Grant Willson

Proceedings Volume 4345, (2001) https://doi.org/10.1117/12.436829

KEYWORDS: Polymers, Photoresist materials, Molecules, Photoresist developing, Lithography, Computer simulations, Polymer thin films, 3D modeling, Scanning electron microscopy, Mathematical modeling

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Proceedings Article | 23 June 2000 Paper

Recent advances in a molecular level lithography simulation

Gerard Schmid, Vivek Singh, Lewis Flanagin, Michael Stewart, Sean Burns, C. Grant Willson

Proceedings Volume 3999, (2000) https://doi.org/10.1117/12.388354

KEYWORDS: Polymers, Computer simulations, Molecules, Diffusion, Lithography, Monte Carlo methods, Photoresist materials, Performance modeling, Deep ultraviolet, Polymer thin films

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Showing 5 of 17 publications

SPIE Conference Volume | 16 March 2009

Design for Manufacturability through Design-Process Integration III

SPIE Conference Volume | 9 April 2008

Design for Manufacturability through Design-Process Integration II

SPIE Conference Volume | 15 March 2007

Design for Manufacturability through Design-Process Integration

SPIE Conference Volume | 10 March 2006

Design and Process Integration for Microelectronic Manufacturing IV

Conference Committee Involvement (24)

DTCO and Computational Patterning IV

23 February 2025 | San Jose, California, United States

DTCO and Computational Patterning III

26 February 2024 | San Jose, California, United States

DTCO and Computational Patterning II

27 February 2023 | San Jose, California, United States

DTCO and Computational Patterning

26 April 2022 | San Jose, California, United States

Design-Technology Co-optimization XV

22 February 2021 | Online Only, California, United States

Design-Process-Technology Co-optimization for Manufacturability XIV

26 February 2020 | San Jose, California, United States

Design-Process-Technology Co-optimization for Manufacturability XIII

27 February 2019 | San Jose, California, United States

Design-Process-Technology Co-optimization for Manufacturability XII

28 February 2018 | San Jose, California, United States

Design-Process-Technology Co-optimization for Manufacturability XI

1 March 2017 | San Jose, California, United States

Design-Process-Technology Co-optimization for Manufacturability X

24 February 2016 | San Jose, California, United States

Design-Process-Technology Co-optimization for Manufacturability IX

25 February 2015 | San Jose, California, United States

Design-Process-Technology Co-optimization for Manufacturability VIII

26 February 2014 | San Jose, California, United States

Design for Manufacturability through Design-Process Integration VII

27 February 2013 | San Jose, California, United States

Design for Manufacturability through Design-Process Integration VI

15 February 2012 | San Jose, California, United States

Design for Manufacturability through Design-Process Integration V

2 March 2011 | San Jose, California, United States

Design for Manufacturability through Design-Process Integration IV

24 February 2010 | San Jose, California, United States

Design for Manufacturability through Design-Process Integration III

26 February 2009 | San Jose, California, United States

Design for Manufacturability through Design-Process Integration II

28 February 2008 | San Jose, California, United States

Design for Manufacturability through Design-Process Integration

1 March 2007 | San Jose, California, United States

Design and Process Integration for Microelectronic Manufacturing IV

23 February 2006 | San Jose, California, United States

Design and Process Integration for Microelectronic Manufacturing IV

3 March 2005 | San Jose, California, United States

Design and Process Integration for Microelectronic Manufacturing III

26 February 2004 | Santa Clara, California, United States

Design and Process Integration for Microelectronic Manufacturing II

27 February 2003 | Santa Clara, CA, United States

Design and Process Integration for Microelectronics Manufacturing

6 March 2002 | Santa Clara, CA, United States

Showing 5 of 24 Conference Committees

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