Paper
12 June 2018 Intra-field mask-to-mask overlay, separating the mask writing from the dynamic pellicle contribution
Richard van Haren, Steffen Steinert, Orion Mouraille, Koen D’havé, Leon van Dijk, Ronald Otten, Dirk Beyer
Author Affiliations +
Abstract
The number of masks required to produce an integrated circuit has increased tremendously over the past years. The main reason for this is that a single layer mask exposure and etch was no longer sufficient to meet the required pattern density. A solution was found in the application of multi-patterning steps, including multiple masks, before the final pattern is transferred into the underlying substrate. Consequently, the mask-to-mask contribution as part of the overall on-product (intra-layer) overlay budget could not be neglected anymore. While the tight on-product overlay specifications (< 3-nm) were initially only requested for the intra-layer (e.g. multi Litho Etch Litho Etch) overlay performance, recently these tight requirements are also imposed for the layer-to-layer overlay. Recently, we reported on an extensive study in which the mask-to-mask overlay contribution as determined by the PROVE mask registration tool was correlated with actual on-wafer measurements. Two ASML BMMO (Baseliner Matched Machine Overlay) masks were used for this purpose. Initially, no pellicles were mounted onto the masks. An excellent correlation was found between the measurements on the PROVE tool and the on-wafer results reaching R2 < 0.96 with an accuracy of 0.58-nm. The accuracy level can be further improved since all underlying contributors were identified. It was concluded that the expected overlay as measured on-wafer can be fully determined by off-line registration measurements only. An important note is that the off-line registration measurements on the PROVE tool are performed in a static mode, while the exposures on an ASML TWINSCANTM are performed in a dynamic (scanning) mode. No impact was observed since both masks were not equipped with a pellicle. One can expect that also for the case where both masks are equipped with a pellicle of the same type, the impact is negligible. The reason for this is that all pellicle induced errors are likely to be the same for both masks in scanning mode and will cancel out in the overlay. However, the correlation between offline mask-to-mask overlay measurements and on-wafer measurements is expected to deteriorate when only one of the masks is equipped with a pellicle. Evidence for this was already found even when we operated the scanner in slow scan mode. In this work, we have extended the study by considering the impact of a pellicle on one of the masks and how it affects the intra-field overlay. As a logical consequence, it will have an impact on the correlation between the mask-to-mask and the on-wafer overlay measurements. An experimental technique has been developed to isolate the main impact of a scanning pellicle. We show that, in addition to the mask-to-mask writing errors, the pellicle induced errors can be characterized as well. We demonstrate that the correlation is restored when the pellicle contribution is removed from the on-wafer overlay measurements. The impact of the pellicle on the intra-field overlay performance should be treated as a separate overlay contributor that needs to be minimized separately. Calibration and scanner correction capabilities are in place to mitigate the pellicle induced overlay errors.
© (2018) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Richard van Haren, Steffen Steinert, Orion Mouraille, Koen D’havé, Leon van Dijk, Ronald Otten, and Dirk Beyer "Intra-field mask-to-mask overlay, separating the mask writing from the dynamic pellicle contribution", Proc. SPIE 10807, Photomask Japan 2018: XXV Symposium on Photomask and Next-Generation Lithography Mask Technology, 108070K (12 June 2018); https://doi.org/10.1117/12.2500086
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KEYWORDS
Pellicles

Overlay metrology

Reticles

Scanners

Photomasks

Image registration

Semiconducting wafers

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