Process context based wafer level grouping control: an advanced overlay process correction designed for DRAM 1z nm node in high volume manufacturing

Linmiao Zhang; William Susanto; Katsumasa Takahashi; Albert Chen; Tim Tang; Yi Zou; Chenxi Lin; Simon Hastings; Samee Ur Rehman; Manouk Rijpstra; Alfonso Sun

doi:10.1117/12.2552823

20 March 2020 Process context based wafer level grouping control: an advanced overlay process correction designed for DRAM 1z nm node in high volume manufacturing

Linmiao Zhang, William Susanto, Katsumasa Takahashi, Albert Chen, Tim Tang, Yi Zou, Chenxi Lin, Simon Hastings, Samee Ur Rehman, Manouk Rijpstra, Alfonso Sun

Author Affiliations +

Proceedings Volume 11325, Metrology, Inspection, and Process Control for Microlithography XXXIV; 113251O (2020) https://doi.org/10.1117/12.2552823
Event: SPIE Advanced Lithography, 2020, San Jose, California, United States

Abstract

On Product Overlay (OPO) is a critical budget for advanced lithography. LithoInSight (LIS), an ASML application product, has proven to improve the ability of advanced process control (APC) for overlay with accurate fingerprint estimation and optimized scanner correction. It is now often used as Process of Record (PoR) for performing chuck/lot based run-to-run (R2R) control in a High Volume Manufacturing (HVM) environment. In order to further improve the on-product performance given the ever-tightening overlay spec. in advanced nodes, the question of how to reduce wafer-to-wafer process-induced variation has been asked frequently. Studies have shown that the wafer-to-wafer overlay variation is driven by certain critical process contexts. Aiming to bring a solution to the HVM phase, the ASML and Micron Data Science teams developed a Wafer Level Grouping Control (WLGC) methodology to perform overlay control given the process context information. This methodology has been implemented in one of the Micron production fabs, and demonstrated both reduced wafer-to-wafer (W2W) overlay variation and improved device yield on a yield-critical layer for a product from Micron 1z DRAM node.

Conference Presentation

Citation Download Citation

Linmiao Zhang, William Susanto, Katsumasa Takahashi, Albert Chen, Tim Tang, Yi Zou, Chenxi Lin, Simon Hastings, Samee Ur Rehman, Manouk Rijpstra, and Alfonso Sun "Process context based wafer level grouping control: an advanced overlay process correction designed for DRAM 1z nm node in high volume manufacturing", Proc. SPIE 11325, Metrology, Inspection, and Process Control for Microlithography XXXIV, 113251O (20 March 2020); https://doi.org/10.1117/12.2552823

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