Poster + Presentation + Paper
22 February 2021 Mark design challenge of cut layer in FinFet
Author Affiliations +
Conference Poster
Abstract
The requirement of overlay performance, which is determined by alignment process during exposure and overlay measurement process, is getting tighter as technology node shrinks in integrated circuit. Mark design has drawn a lot of attention since appropriately designed marks can guarantee process compatibility and sufficient device performance tracking property. Cut layers are widely used in FinFet to define active area formed by SADP (Self-aligned double patterning) or SAQP (Self-aligned quadruple patterning), of which the mark design is especially challenging for diffusion break layer since it is a cut layer that landing on three dimensional fin structure and will be aligned to. In this paper, mark design of diffusion break layer is investigated, including alignment marks and overlay marks with various substrates and segmentations. It’s recommended that the whole process from mark definition by lithography to final formation of mark after etch should be well taken into consideration during mark design, along with substrate and segmentation to avoid defect and achieve qualified signal as well.
Conference Presentation
© (2021) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Lulu Lai, Yuyang Bian, Shaopeng Chen, Biqiu Liu, Rui Qian, Xiaobo Guo, Cong Zhang, Jun Huang, and Yu Zhang "Mark design challenge of cut layer in FinFet", Proc. SPIE 11611, Metrology, Inspection, and Process Control for Semiconductor Manufacturing XXXV, 116112J (22 February 2021); https://doi.org/10.1117/12.2583567
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KEYWORDS
Fin field effect transistors

Diffusion

Optical alignment

Signal processing

Etching

Integrated circuits

Lithography

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