Design and implementation of 10Gbps SerDes receiver equalizer

Tao Liu; Xin Chen; Lei Wang; Ying Zhang

doi:10.1117/12.2640018

23 May 2022 Design and implementation of 10Gbps SerDes receiver equalizer

Tao Liu, Xin Chen, Lei Wang, Ying Zhang

Proceedings Volume 12254, International Conference on Electronic Information Technology (EIT 2022); 122541W (2022) https://doi.org/10.1117/12.2640018
Event: International Conference on Electronic Information Technology (EIT 2022), 2022, Chengdu, China

Abstract

Aiming at the 17dB loss problem in the 10Gbps rate transmission channel in SerDes, this article implements an equalizer of SerDes receiver with TSMC 28nm CMOS technology. At first, a structure of continuous time linear equalizer (CTLE) is adopted to compensate for the loss in the channel. However, due to the inter-symbol interference (ISI) of signals passing through channel, the phenomenon of serious tailing occurs. Therefore, a 4-tap finite impulse response (FIR) decision feedback equalizer (DFE) is added to eliminate ISI post-cursor. Based on the circuit schematic, the simulation results show that the proposed equalizer structure can effectively compensate for the 17dB channel loss and eliminate the ISI post-cursor. The equalized eye width reaches 0.95UI at 0.9V supply.

Citation Download Citation

Tao Liu, Xin Chen, Lei Wang, and Ying Zhang "Design and implementation of 10Gbps SerDes receiver equalizer", Proc. SPIE 12254, International Conference on Electronic Information Technology (EIT 2022), 122541W (23 May 2022); https://doi.org/10.1117/12.2640018

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