Chip cluster registration technique for increased throughput in e-beam direct writing

John F. Bass; Michael J. Butler

doi:10.1117/12.20156

1 May 1990 Chip cluster registration technique for increased throughput in e-beam direct writing

John F. Bass, Michael J. Butler

Proceedings Volume 1263, Electron-Beam, X-Ray, and Ion-Beam Technology: Submicrometer Lithographies IX; (1990) https://doi.org/10.1117/12.20156
Event: Microlithography '90, 1990, San Jose, CA, United States

Abstract

The use of E-beam lithography for direct writing GaAs device levels is a widely accepted technique in the manufacture of discrete PET and MMICs. Throughput in these applications is a function of wafer size, number of chips, resist sensitivity, available beam current, pattern density and the inherent tool overheads of stage movement and registration time. Of these, chip registration can be the single most time consuming component. Techniques have been developed that minimize the writing time while maintaining the required level and pattern accuracy. These techniques include using multiple beam currents and multiple field sizes for high and low resolution areas and using optical exposure of less critical areas in a mixed lithography scheme. In this paper we present a technique of cluster registration that reduces registration time by as much as 75 percent. Resultant data illustrate no loss of line width control or placement accuracy utilizing this procedure. We describe software techniques and procedures that provide automatic creation of job control files and system executive control files yielding full turn key operation of a Cambridge EBMF 10.5 E-beam pattern generator. In addition, we discuss the use of this lithography tool for automated line width metrology of the resultant lifted off gate.

Citation Download Citation

John F. Bass and Michael J. Butler "Chip cluster registration technique for increased throughput in e-beam direct writing", Proc. SPIE 1263, Electron-Beam, X-Ray, and Ion-Beam Technology: Submicrometer Lithographies IX, (1 May 1990); https://doi.org/10.1117/12.20156

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KEYWORDS

Semiconducting wafers

X-ray technology

Lithography

Control systems

X-ray lithography

X-rays

Optical alignment

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