Optimal design of phase-locked amplifier based on FPGA

Lintao Yu; Haoran Li

doi:10.1117/12.2685620

28 July 2023 Optimal design of phase-locked amplifier based on FPGA

Lintao Yu, Haoran Li

Proceedings Volume 12716, Third International Conference on Digital Signal and Computer Communications (DSCC 2023); 127160Z (2023) https://doi.org/10.1117/12.2685620
Event: Third International Conference on Digital Signal and Computer Communications (DSCC 2023), 2023, Xi'an, China

Abstract

As an effective technology for precise detection of weak signals, phase-locked amplifiers are widely used in various fields. Field programmable gate array (FPGA) can improve data processing speed by virtue of its large-scale parallel data processing capability and pipeline technology, so it has obvious advantages in digital signal processing. The design of digital phase-locked amplifier based on FPGA can reach a high level in speed and accuracy. The digital low-pass filter in the traditional phase-locked amplifier is a combination of adder and multiplier in structure. Because in FPGA, the multiplication operation needs to consume a lot of system hardware resources, this paper proposes to use the distributed algorithm based on table segmentation technology to realize the digital phase-locked amplifier, which optimizes the problem of the large resource occupation of the traditional multiply-plus phase-locked amplifier, and solves the problem of the shortage of multiplier resources, It saves on-chip resources of FPGA and makes the phase-locked amplification technology easier to implement on FPGA.

Citation Download Citation

Lintao Yu and Haoran Li "Optimal design of phase-locked amplifier based on FPGA", Proc. SPIE 12716, Third International Conference on Digital Signal and Computer Communications (DSCC 2023), 127160Z (28 July 2023); https://doi.org/10.1117/12.2685620

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