Poster + Paper
23 August 2024 The Black Hole Explorer: back end electronics
Author Affiliations +
Conference Poster
Abstract
This paper describes specification and early design of back end signal processing subsystems for the Black Hole Explorer (BHEX) Very Long Baseline Interferometry (VLBI) space telescope. The“back end” consists of two subsystems. First, the block downconveter (BDC) is a heterodyne system that performs a frequency translation of the analog signal from IF to baseband and amplifies and filters it for digitization. Second, the digital back end (DBE) samples the analog signal with an analog-to-digital converters (ADC) and digitally processes the data stream formatting them to the VLBI “VDIF” standard and converting to Ethernet packets for 100 gigabitper-second (Gb/s) Ethernet transport to the optical downlink system. Both the BDC and the DBE for BHEX support eight channels of 4.096 GHz bandwidth each, for a total processed bandwidth of 32.768 GHz. The BHEX back end benefits from mature terrestrial back end heritage, described in some detail. The BHEX back end itself is in the early stages of design, with requirements, interface specifications, and component trade studies well advanced. The aim is to build a prototype using terrestrial grade parts which are available in functionally identical space grade equivalents, and to use this prototype to advance the back end Technology Readiness Level (TRL) preparing for a Small Explorer (SMEX) proposal in 2025.
(2024) Published by SPIE. Downloading of the abstract is permitted for personal use only.
Ranjani Srinivasan, Jonathan Weintroub, Rick Raffanti, Bryan Bilyeu, Thomas Gauron, John Test, Elliot Richards, Manuel Fernandez, Mark Freeman, Peter Cheimets, Mauricio Gendelman, Kari Haworth, Janice Houston, Michael D. Johnson, Emilia Mamani, Daniel Marrone, Ariel L. Pola, and Jade Wang "The Black Hole Explorer: back end electronics", Proc. SPIE 13092, Space Telescopes and Instrumentation 2024: Optical, Infrared, and Millimeter Wave, 130926V (23 August 2024); https://doi.org/10.1117/12.3020729
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KEYWORDS
Field programmable gate arrays

Analog to digital converters

Analog electronics

Receivers

Design

Signal processing

Digital signal processing

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