FIR filter implementation using bit-serial arithmetic and partial summation trees

S. Gibb; P. J. W. Graumann; Laurence E. Turner

doi:10.1117/12.255462

22 October 1996 FIR filter implementation using bit-serial arithmetic and partial summation trees

S. Gibb, P. J. W. Graumann, Laurence E. Turner

Proceedings Volume 2846, Advanced Signal Processing Algorithms, Architectures, and Implementations VI; (1996) https://doi.org/10.1117/12.255462
Event: SPIE's 1996 International Symposium on Optical Science, Engineering, and Instrumentation, 1996, Denver, CO, United States

Abstract

An architecture which efficiently implements a fixed coefficient FIR filter using pipelined bit-serial arithmetic is described. A specialized multiplier decomposition exploiting multiplier coefficient similarities is used to obtain a reduced hardware area implementation. A design methodology which supports the conversion of a frequency response specification into a gate level implementation of the filter is presented. An 89 tap FIR filter meeting a multi-band frequency response specification, with 16 bit internal data precision and a sample rate of 1.6 GHz for parallel input and output data is implemented on a single XILINX 4005PG156 FPGA device.

Citation Download Citation

S. Gibb, P. J. W. Graumann, and Laurence E. Turner "FIR filter implementation using bit-serial arithmetic and partial summation trees", Proc. SPIE 2846, Advanced Signal Processing Algorithms, Architectures, and Implementations VI, (22 October 1996); https://doi.org/10.1117/12.255462

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