Implemenation of a color edge detection operator in FPGA architecture

Hassane Guermoud; Serge Weber; Yves Berviller; Etienne Tisserand

doi:10.1117/12.266350

7 February 1997 Implemenation of a color edge detection operator in FPGA architecture

Hassane Guermoud, Serge Weber, Yves Berviller, Etienne Tisserand

Proceedings Volume 2949, Imaging Sciences and Display Technologies; (1997) https://doi.org/10.1117/12.266350
Event: Advanced Imaging and Network Technologies, 1996, Berlin, Germany

Abstract

In this article we present the study of a color edge extractor operator. We make an evaluation of the costs in terms of die size and latency time in the case of an implementation in F.P.G.A. This makes it possible to operate at 25 images/second and thus satisfy a lot of industrial applications.

Citation Download Citation

Hassane Guermoud, Serge Weber, Yves Berviller, and Etienne Tisserand "Implemenation of a color edge detection operator in FPGA architecture", Proc. SPIE 2949, Imaging Sciences and Display Technologies, (7 February 1997); https://doi.org/10.1117/12.266350

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