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7 July 1997 Process optimization by reducing I-D bias for 0.25-μm logic devices
Ki-Yeop Park, Byoung-Il Choi, Won-Kyu Lee, Chul-Gi Ko
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Proceedings Volume 3051, Optical Microlithography X; (1997) https://doi.org/10.1117/12.276017
Event: Microlithography '97, 1997, Santa Clara, CA, United States
Abstract
The print bias between isolated and dense resist pattern (I- D bias) which is originated from the optical proximity effect, is one of the major issues for the processing of randomly arrayed and complicatedly structured logic devices designed with the smaller features than ever. In this study, the characteristics of I-D bias which is related to not only optical parameters but also resist processing parameters were investigated quantitatively through the way of experiment and simulation. Examined processing parameters were as follows: numerical aperture and partial coherence factor ((sigma) ) as the exposure parameters; the ratio of line to space width (duty ratio) as the mask parameter; resist thickness, prebake temperature and post exposure back temperature as the resist processing parameters. The experiments were reviewed in simulation tools such as Prolith2+ and SOLID-C. And the resist patterns were acquired using DUV exposure tool with various kinds of resist.
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Ki-Yeop Park, Byoung-Il Choi, Won-Kyu Lee, and Chul-Gi Ko "Process optimization by reducing I-D bias for 0.25-μm logic devices", Proc. SPIE 3051, Optical Microlithography X, (7 July 1997); https://doi.org/10.1117/12.276017
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KEYWORDS
Logic devices
Photoresist processing
Deep ultraviolet
Structural design
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