Sheet resistance requirements for the source/drain regions of 0.11-um gate length CMOS technology

Manoj Mehrotra; Amitava Chatterjee; Ih-Chin Chen

doi:10.1117/12.284588

27 August 1997 Sheet resistance requirements for the source/drain regions of 0.11-μm gate length CMOS technology

Manoj Mehrotra, Amitava Chatterjee, Ih-Chin Chen

Proceedings Volume 3212, Microelectronic Device Technology; (1997) https://doi.org/10.1117/12.284588
Event: Microelectronic Manufacturing, 1997, Austin, TX, United States

Abstract

MOSFETs with partially contacted source/drain regions are often used in ASIC designs in order to improve the layout density of the gate arrays. Such contacting scheme adds resistance to current flow which reduces transistor current and hence degrades device performance. This paper presents the effect of source/drain region sheet resistance on the performance figure of merit (FOM) for partially contacted deep submicron CMOS transistors. These partially contacted transistors are modeled as distributed network of MOSFETs and resistances in order to study the impact of source/drain region resistance on drive currents. It is found that the source/drain sheet resistance plays a significant role in determining the FOM of these transistors. For example, our modeling shows that for 0.11 micrometer technology, a source/drain region sheet resistance of only 7 Ohms/sq. results in 1% degradation in performance FOM for diagonally contacted transistors with W/L of 20 and W_s of 0.27 micrometer.

Citation Download Citation

Manoj Mehrotra, Amitava Chatterjee, and Ih-Chin Chen "Sheet resistance requirements for the source/drain regions of 0.11-μm gate length CMOS technology", Proc. SPIE 3212, Microelectronic Device Technology, (27 August 1997); https://doi.org/10.1117/12.284588

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