Data path allocation for low power in high-level synthesis

Yu Hong Zheng; Ching Chuen Jong; Hongwei Zhu

doi:10.1117/12.405402

24 October 2000 Data path allocation for low power in high-level synthesis

Yu Hong Zheng, Ching Chuen Jong, Hongwei Zhu

Proceedings Volume 4228, Design, Modeling, and Simulation in Microelectronics; (2000) https://doi.org/10.1117/12.405402
Event: International Symposium on Microelectronics and Assembly, 2000, Singapore, Singapore

Abstract

This paper presents an approach for data path allocation in high-level synthesis aiming at power reduction. In this approach, the register allocation and module allocation are performed in the same phase in polynomial time. The power consumption is reduced by minimizing the functional switching and switched capacitance of the implementation architecture. The experimental results confirm the viability and usefulness of the approach in minimizing power consumption while keeping the number of registers and interconnections to the optimal.

Citation Download Citation

Yu Hong Zheng, Ching Chuen Jong, and Hongwei Zhu "Data path allocation for low power in high-level synthesis", Proc. SPIE 4228, Design, Modeling, and Simulation in Microelectronics, (24 October 2000); https://doi.org/10.1117/12.405402

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