Design and analysis of RAM transparent March test for BIST implementation

Serge N. Demidenko; Scott A. Henderson

doi:10.1117/12.405434

24 October 2000 Design and analysis of RAM transparent March test for BIST implementation

Serge N. Demidenko, Scott A. Henderson

Proceedings Volume 4228, Design, Modeling, and Simulation in Microelectronics; (2000) https://doi.org/10.1117/12.405434
Event: International Symposium on Microelectronics and Assembly, 2000, Singapore, Singapore

Abstract

New transparent memory test algorithms for semiconductor memory are presented in the paper along with the modified memory testing simulation package MAP. The test algorithms allow detecting memory read errors - the error type that was not covered in the previous research.

Citation Download Citation

Serge N. Demidenko and Scott A. Henderson "Design and analysis of RAM transparent March test for BIST implementation", Proc. SPIE 4228, Design, Modeling, and Simulation in Microelectronics, (24 October 2000); https://doi.org/10.1117/12.405434

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