Paper
2 July 2002 Single Instruction Set Architectures for Image Processing
Phillip A. Laplante, William Gilreath
Author Affiliations +
Proceedings Volume 4867, Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications IV; (2002) https://doi.org/10.1117/12.455451
Event: ITCom 2002: The Convergence of Information Technologies and Communications, 2002, Boston, MA, United States
Abstract
For more than fifty years, computer engineers have sought to construct minimal computers using only a single instruction computer. While it might appear to be a simple academic exercise, remarkably, a rich computation paradigm can be developed using this approach, with important applications and implications in reconfigurable, chemical, optical and biological computing. More recently, the widespread use of the Field Programmable Gate Array (FPGA) has made such an approach not only desirable, but also practical. In this paper the history and motivation behind single instruction or one instruction computing (OISC) is reviewed. It is then shown how the paradigm can be used to implement a variety of imaging operations efficiently. Finally, a practical application and future work in languages and tools are presented.
© (2002) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Phillip A. Laplante and William Gilreath "Single Instruction Set Architectures for Image Processing", Proc. SPIE 4867, Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications IV, (2 July 2002); https://doi.org/10.1117/12.455451
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Cited by 5 scholarly publications.
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KEYWORDS
Field programmable gate arrays

Logic

Image processing

Chemical elements

Computer architecture

Standards development

Image filtering

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