MPLS switch architecture supporting Diffserv for high-speed switching and QoS

Tae-Won Lee; Young-Chul Kim; Mike Myung-Ok Lee

doi:10.1117/12.528585

30 March 2004 MPLS switch architecture supporting Diffserv for high-speed switching and QoS

Tae-Won Lee, Young-Chul Kim, Mike Myung-Ok Lee

Proceedings Volume 5274, Microelectronics: Design, Technology, and Packaging; (2004) https://doi.org/10.1117/12.528585
Event: Microelectronics, MEMS, and Nanotechnology, 2003, Perth, Australia

Abstract

In this paper, we propose the architecture of the MPLS switch supporting Differentiated Services in the MPLS-based network. The traffic conditioner consists of a classifier, a meter, and a marker. The VOQ-PHB module which combines input queue with each PHB queue is implemented to utilize the resources more efficiently, employing the Priority-iSLIP scheduling algorithm to support high-speed switching. The proposed MPLS switch architecture is modeled and synthesized by Very High Speed Integrated Circuits Hardware Description Language (VHDL), verified and then implemented by commercialized CAD tools to justify the validity of the proposed hardware architecture.

Citation Download Citation

Tae-Won Lee, Young-Chul Kim, and Mike Myung-Ok Lee "MPLS switch architecture supporting Diffserv for high-speed switching and QoS", Proc. SPIE 5274, Microelectronics: Design, Technology, and Packaging, (30 March 2004); https://doi.org/10.1117/12.528585

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