Paper
3 April 2012 In-line metrology of 3D interconnect processes
Author Affiliations +
Abstract
The continuous development of three-dimensional chip/wafer stacking technology has created the metrology requirements for in-line 3D manufacturing processes. This paper summarizes the developing metrology that has been used during via-middle & via-last TSV process development at ITRI (Industrial Technology Research Institute). An IR metrology tool including broadband infrared microscopic imaging module and a specific infrared laser confocal module is developed for the thinned wafers thickness measurement with spatial resolution of 0.5 μm. An existing spectral reflectometer is used and enhanced by implementing novel theoretical model and measurement algorithm for HDTSV inspection. It is capable of measuring via depth/bottom roughness/bottom profile in one shot measurement. A metrology module based on two sets of dual-channel capacitive sensors for metallization film thickness measurement is applied to make critical process control in the fab. We will share real metrology results and discuss possible solutions for 3D interconnect processing.
© (2012) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Y. S. Ku, D. M. Shyu, P. Y. Chang, and W. T. Hsu "In-line metrology of 3D interconnect processes", Proc. SPIE 8324, Metrology, Inspection, and Process Control for Microlithography XXVI, 832411 (3 April 2012); https://doi.org/10.1117/12.915810
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Cited by 2 scholarly publications.
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KEYWORDS
Semiconducting wafers

Metrology

3D metrology

Silicon

Reflectivity

Copper

Metals

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