Analysis Of Overlay Distortion Patterns

John D. Armitage Jr.; Joseph P. Kirk

doi:10.1117/12.968368

1 January 1988 Analysis Of Overlay Distortion Patterns

John D. Armitage Jr., Joseph P. Kirk

Proceedings Volume 0921, Integrated Circuit Metrology, Inspection, and Process Control II; (1988) https://doi.org/10.1117/12.968368
Event: Santa Clara Symposium on Microlithography, 1988, Santa Clara, CA, United States

Abstract

A comprehensive geometrical approach is presented for the least-squares analysis of overlay distortion patterns into useful, physically meaningful systematic distortion subpatterns and an essentially non-systematic residue. A scheme of generally useful distortion sub-patterns is presented in graphic and algorithmic form; some of these sub-patterns are additions to those already in widespread use. A graphic and geometric approach is emphasized rather than an algebraic or statistical approach, and an example illustrates the value in utilizing the pattern-detecting ability of the eye-brain system. The conditions are described under which different distortion sub-patterns may interact, possibly leading to misleading or erroneous conclusions about the types and amounts of different distortions present. Examples of typical interaction situations are given, and recommendations are made for analytic procedures to avoid misinterpretation. It is noted that the lower-order distortion patterns preserve straight-line linearity, but that higher-order distortion may result in straight lines becoming curved. The principle of least-squares analysis is outlined and a simple polynomial data-fitting example is used to illustrate the method. Algorithms are presented for least-squares distortion analysis of overlay patterns, and an APL2 program is given to show how this may easily be implemented on a digital computer. The appendix extends the treatment to cases where small-angle approximation is not permissible.

Citation Download Citation

John D. Armitage Jr. and Joseph P. Kirk "Analysis Of Overlay Distortion Patterns", Proc. SPIE 0921, Integrated Circuit Metrology, Inspection, and Process Control II, (1 January 1988); https://doi.org/10.1117/12.968368

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