This PDF file contains the front matter associated with SPIE Proceedings Volume 9256, including the Title Page, Copyright information, Table of Contents, Introduction (if any), and Conference Committee listing.

The impact of various mask parameters on CDU combined in a total mask budget is presented, for 22 nm lines, for reticles used for NXE:3300 qualification. Apart from the standard mask CD measurements, actinic spectrometry of multilayer is used to qualify reflectance uniformity over the image field; advanced 3D metrology is applied for absorber profile characterization including absorber height and side wall angle. The predicted mask impact on CDU is verified using actual exposure data collected on multiple NXE:3300 scanners. Mask 3D effects are addressed, manifesting themselves in best focus shifts for different structures exposed with off-axis illumination. Experimental NXE:3300 results for 16 nm dense lines and 20 nm (semi-)isolated spaces are shown: best focus range reaches 24 nm. A mitigation strategy by absorber height optimization is proposed based on experimental results of a special mask with varying absorber heights. Further development of a black image border for EUV mask is considered. The image border is a pattern free area surrounding image field preventing exposure the image field neighborhood on wafer. Normal EUV absorber is not suitable for this purpose as it has 1-3% EUV reflectance. A current solution is etching of ML down to substrate reducing EUV reflectance to <0.05%. A next step in the development of the black border is the reduction of DUV Out-of-Band reflectance (<1.5%) in order to cope with DUV light present in EUV scanners. Promising results achieved in this direction are shown.

Standard OPC models consist of a physical optical model and an empirical resist model. The resist model compensates the optical model imprecision on top of modeling resist development. The optical model imprecision may result from mask topography effects and real mask information including mask ebeam writing and mask process contributions. For advanced technology nodes, significant progress has been made to model mask topography to improve optical model accuracy. However, mask information is difficult to decorrelate from standard OPC model. Our goal is to establish an accurate mask model through a dedicated calibration exercise. In this paper, we present a flow to calibrate an accurate mask enabling its implementation. The study covers the different effects that should be embedded in the mask model as well as the experiment required to model them.

In recent years, photomask resist strip and cleaning technology development was substantially driven by the industry's need to prevent surface haze formation through the elimination of sulfuric acid and ammonium hydroxide from these processes. As a result, conventional SPM (H₂SO₄ + H₂O₂) was replaced with Ozone water (DIO₃) for resist stripping and organic removal to eliminate chemical haze formation [1, 2]. However, it has been shown that DIO₃ basted strip and clean process causes oxidative degradation of photomask materials [3, 4]. Such material damage can affect optical properties of funcitional mask layers, causeing CD line-width, phase, transmission and reflection changes, adversely affecting image transfer during the Lithography process. To overcome Ozone induced surface damage, SUSS MicroTec successfully developed a highly efficient strip process, where photolysis of DIO3 is leading to highly reactive hydroxyl radical formation, as the main contribution to hydrocarbon removal without surface damage [5]. This technology has been further extended to a final clean process, which is utilizing pure DI water for residual organic material removal during final clean [6]. Recently, SUS MicroTec did also successfully release strip and clean processes which completely remove NH4OH, eliminating any chemicals known today to induce haze [7]. In this paper we show the benefits of these new technologies for highly efficient sulfate and ammonium free stripping and cleaning processes.

AIMS^™ is mainly used in photomask industry for verifying the impact of mask defects on wafer CD in DUV lithography process. AIMS verification is used for D2D configuration, where two AIMS images, reference and defect, are captured and compared. Criticality of defects is identified using a number of criteria. As photomasks with aggressive OPC and sub-resolution assist features (SRAFs) are manufactured in production environment, it is required to save time for identifying reference pattern and capturing the AIMS image from the mask. If it is a single die mask, such technology is truly not applicable. A solution is to use AIMS die-to-database (D2DB) methodology which compares AIMS defect image with simulated reference image from mask design data. In general, simulation needs calibration with AIMS images. Because there is the difference between an AIMS image except a defect and a reference image, the difference must be compensated. When it is successfully compensated, AIMS D2DB doesn’t need any reference images, but requires some AIMS images for calibration. Our approach to AIMS D2DB without calibration image is systematic comparison of several AIMS images and to fix optical condition parameters for reducing calibration time. And we tried to calibrate using defect AIMS image to this approach. In this paper, we discuss performance of AIMS D2DB simulation without calibration images.

Because mask patterning quality of CD uniformity, MTT, registration and smaller assist feature size is important for wafer patterning, the higher exposure dose and complex pattern design will be necessary. It is the reason why the faster and more accurate e-beam mask writer is needed for future design node. Multi-beam mask writer is the most promising new e-beam mask writer technology for future sub-10nm device mask patterning to solve the pattern quality issue and writing time problem. In this report, the technical challenges of multi-beam mask writer are discussed by comparison with problems of current VSB e-beam mask writer. Comparing with e-beam mask writer which has the critical issues of beam size and position control, the application of entirely different methods and techniques of CD and position control is essential for multi-beam mask writer which has new architecture and writing strategy. Using the simulation method, we present the different challenges between VSB and multi-beam mask writer. And there are many important technical requirements to achieve expected specification of multi-beam mask writer. To understand such requirements, the patterning simulation and mathematical calculation are done for analysis. Based on the patterning simulation, the detail technical requirements and issues of multi-beam mask writer are achieved. Consequently, we suggest the direction of multi-beam mask writer development in terms of technical challenges and requirements.

EBM-9000 equipped with new features such as new electron optics, high current density (800A/cm²) and high speed deflection control has been developed for the 11nm technology node(tn) (half pitch (hp) 16nm). Also in parallel of aggressive introduction of new technologies, EBM-9000 inherits the 50kV variable shaped electron beam / vector scan architecture, continuous stage motion and VSB-12 data format handling from the preceding EBM series to maintain high reliability accepted by many customers. This paper will report our technical challenges and results obtained through the development.

ArF immersion lithography combined with double patterning has been used for fabricating below half pitch 40nm devices. However, when pattern size shrinks below 20nm, we must use new technology like quadruple patterning process or next generation lithography (NGL) solutions. Moreover, with change in lithography tool, next generation mask production will be needed. According to ITRS 2013, fabrication of finer patterns less than 15nm will be required on mask plate in NGL mask production 5 years later [1]. In order to fabricate finer patterns on mask, higher resolution EB mask writer and high performance fabrication process will be required. In a previous study, we investigated a potential of mask fabrication process for finer patterning and achieved 17nm dense line pattern on mask plate by using VSB (Variable Shaped Beam) type EB mask writer and chemically amplified resist [2][3]. After a further investigation, we constructed higher performance mask process by using new EB mask writer EBM9000. EBM9000 is the equipment supporting hp16nm generation's photomask production and has high accuracy and high throughput. As a result, we achieved 15.5nm pattern on mask with high productivity. Moreover, from evaluation of isolated pattern, we proved that current mask process has the capability for sub-10nm pattern. These results show that the performance of current mask fabrication process have the potential to fabricate the next-generation mask.

In our previous work, we reported the static portion of the surface charging on EBM-8000 and compared it with that on EBM-6000. The scope of this paper is to report the analysis of charging decay component on EBM-8000 and compare it with EBM-6000. We confirmed that our fundamental modeling scheme of the charging decay worked well on EBM-8000 as well as on EBM-6000. However, we found totally different charging decay behaviors between EBM-8000 and EBM-6000. To explain the results, we propose a conceptual model of the charging decay phenomena both on EBM-8000 and EBM-6000.

Novel photo-lithography is newly proposed named built-in lens mask lithography. The method emulates optical propagation plane in exposure system using binary transmittance and phase mask instead of projection lens. The performance of the built-in lens mask lithography is studied by numerical simulation and experimental study using conventional proximity exposure system. The result shows resolution enhancement in deep focus plane.

In this report, we compared the lithographic performances between the conventional positive tone development (PTD) process and the negative tone development (NTD) process, using the lithography simulation. We selected the MoSi-binary mask and conventional 6% attenuated phase shift mask as mask materials. The lithographic performance was evaluated and compared after applying the optical proximity correction (OPC). The evaluation items of lithographic performance were the aerial image profile, the aerial image contrast, normalized image log slope (NILS), mask error enhancement factor (MEEF), and the bossung curves, etc. The designs for the evaluation were selected the simple contact hole and the metal layer sample design.

From late 1990s to 2000s, the demands for Flat Panel Displays (FPDs), represented by Liquid Crystal Displays (LCDs), were mainly for larger size and lower price. Consequently, the development of FPD exposure tools was focused on expansion of exposure area and high throughput. Today, however, due to rapid growth of application for mobile devices, such as Smartphones and Tablet PCs, high resolution FPDs are being needed, and exposure tools are being demanded to constantly print finer pattern than before. In order To meet such needs, in 2013, Canon has released MPAsp-E813 and MPAsp-H803 series, which can resolve 2.0μm Line and Space (L and S) pattern and 2.5μm Contact Hole (CH) pattern. However, FPD resolution for mobile devices is still getting higher and higher, and now extremely high resolution of 1.5μm L and S is already in great demand.

As design rules of lithography shrink: accuracy and precision of Critical Dimension (CD) and controllability of hard OPCed patterns are required in semiconductor production. Critical Dimension Scanning Electron Microscopes (CD SEM) are essential tools to confirm the quality of a mask such as CD control; CD uniformity and CD mean to target (MTT). Basically, Repeatability and Reproducibility (R and R) performance depends on the length of Region of Interest (ROI). Therefore, the measured CD can easily fluctuate in cases of extremely narrow regions of OPCed patterns. With that premise, it is very difficult to define MTT and uniformity of complex OPCed masks using the conventional SEM measurement approach. To overcome these difficulties, we evaluated Design Based Metrology (DBM) using Large Field Of View (LFOV) of CD-SEM. DBM can standardize measurement points and positions within LFOV based on the inflection/jog of OPCed patterns. Thus, DBM has realized several thousand multi ROI measurements with average CD. This new measurement technique can remove local CD errors and improved statistical methodology of the entire mask to enhance the representativeness of global CD uniformity. With this study we confirmed this new technique as a more reliable methodology in complex OPCed patterns compared to conventional technology. This paper summarizes the experiments of DBM with LFOV using various types of the patterns and compares them with current CD SEM methods.

In recent years, 193nm immersion lithography has been extended instead of adopting EUV lithography. And multi-patterning technology is now widely applied, which requires tighter specification as the pattern size gets smaller on advanced semiconductor devices. Regarding the mask registration metrology, it is necessary to consider some difficult challenges like tight repeatability and complex In-Die pattern measurement. In this study, the registration measurement capability was investigated on new registration metrology tool IPRO5+, and new measurement method called Model-Based measurement was evaluated. And the performance and the prospect for advanced technology masks of the IPRO5+ were discussed based on the evaluation results.

193nm immersion lithography is the mainstream production technology for the 20nm and 14nm logic nodes. Multi-patterning of an increasing number of critical layers puts extreme pressure on wafer intra-field overlay, to which mask registration error is a major contributor [1]. The International Technology Roadmap for Semiconductors (ITRS [2]) requests a registration error below 4 nm for each mask of a multi-patterning set forming one layer on the wafer. For mask metrology at the 20nm and 14nm logic nodes, maintaining a precision-to-tolerance (P/T) ratio below 0.25 will be very challenging. Full characterization of mask registration errors in the active area of the die will become mandatory. It is well-known that differences in pattern density and asymmetries in the immediate neighborhood of a feature give rise to apparent shifts in position when measured by optical metrology systems, so-called optical proximity effects. These effects can easily be similar in magnitude to real mask placement errors, and uncorrected can result in mis-qualification of the mask. Metrology results from KLA-Tencor’s next generation mask metrology system are reported, applying a model-based algorithm [3] which includes corrections for proximity errors. The proximity corrected, model-based measurements are compared to standard measurements and a methodology presented that verifies the correction performance of the new algorithm.

In next generation lithography (NGL) for the 1x nm node and beyond, the three dimensional (3D) shape measurements such as side wall angle (SWA) and height of feature on photomask become more critical for the process control. Until today, AFM (Atomic Force Microscope), X-SEM (cross-section Scanning Electron Microscope) and TEM (Transmission Electron Microscope) tools are normally used for 3D measurements, however, these techniques require time-consuming preparation and observation. And both X-SEM and TEM are destructive measurement techniques. This paper presents a technology for quick and non-destructive 3D shape analysis using multi-channel detector MVM-SEM (Multi Vision Metrology SEM), and also reports its accuracy and precision.

EUV lithography is currently the favorite and most promising candidate among the next generation lithography (NGL) technologies. Decade ago the NGL was supposed to be used for 45 nm technology node. Due to introduction of immersion 193nm lithography, double/triple patterning and further techniques, the 193 nm lithography capabilities was greatly improved, so it is expected to be used successfully depending on business decision of the end user down to 10 nm logic. Subsequent technology node will require EUV or DSA alternative technology. Manufacturing and especially process development for EUV technology requires significant number of unique processes, in several cases performed at dedicated tools. Currently several of these tools as e.g. EUV AIMS or actinic reflectometer are not available on site yet. The process development is done using external services /tools with impact on the single unit process development timeline and the uncertainty of the process performance estimation, therefore compromises in process development, caused by assumption about similarities between optical and EUV mask made in experiment planning and omitting of tests are further reasons for challenges to unit process development. Increased defect risk and uncertainty in process qualification are just two examples, which can impact mask quality / process development. The aim of this paper is to identify critical aspects of the EUV mask manufacturing with respect to defects on the mask with focus on mask cleaning and defect repair and discuss the impact of the EUV specific requirements on the experiments needed.

Ruthenium (Ru) film used as capping layer in extreme ultraviolet (EUV) mask peeled off after annealing and in-situ UV (IUV) cleaning. We investigated Ru peeling and found out that the mechanical stress caused by the formation of Si oxide due to the penetration of oxygen atoms from ambient or cleaning media to top-Si of ML is the root cause for the problem. To support our experimental results, we developed a numerical model of finite element method (FEM) using commercial software (ABAQUS™) to calculate the stress and displacement forced on the capping layer. By using this model, we could observe that the displacement agrees well with the actual results measured from the transmission electron microscopy (TEM) image. Using the ion beam deposition (IBD) tool at SEMATECH, we developed four new types of alternative capping materials (RuA, RuB, B₄C, B₄C-buffered Ru). The durability of each new alternative capping layer observed by experiment was better than that of conventional Ru. The stress and displacement calculated from each new alternative capping layer, using modeling, also agreed well with the experimental results. A new EUV mask structure is proposed, inserting a layer of B₄C (B₄C-buffered Ru) at the interface between the capping layer (Ru) and the top-Si layer. The modeling results showed that the maximum displacement and bending stress observed from the B₄C-buffered Ru are significantly lower than that of single capping layer cases. The durability investigated from the experiment also showed that the B₄C-buffered structure is at least 3X stronger than that of conventional Ru.

It is now well established that extremely ultraviolet (EUV) mask multilayer roughness can lead to wafer-plane line-edge roughness (LER) in lithography tools. It is also evident that this same effect leads to sensor plane variability in inspection tools. This is true for both patterned mask and mask blank inspection. Here we evaluate mask roughness specifications explicitly from the actinic inspection perspective. The mask roughness requirement resulting from this analysis are consistent with previously described requirements based on lithographic LER. In addition to model-based analysis, we also consider the characterization of multilayer mask roughness and evaluate the validity of using atomic force microscopy (AFM) based measurements by direct comparison to EUV scatterometry measurements as well as aerial image measurements on a series of high quality EUV masks. The results demonstrate a significant discrepancy between AFM results and true EUV roughness as measured by actinic scattering.

Defects in the EUV mask blank are one of the largest hurdles to achieving manufacturing readiness of EUV masks. For defect-free masks, the obvious approach is to order blanks that do not have defects or to shift the pattern so that remaining defects do not create a printed defect on wafer. The approach during development should be different. At this learning phase, it is wise to study the defects as they occur naturally on the EUV mask blank. This paper outlines a comprehensive approach to building a mask specifically to showcase the native defects so that they can be studied and repairs can be attempted. The method applied to mask build, defect inspection and characterization will be reviewed in detail. Printability of the mask defects of interest are characterized using both wafer printing and EUV microscope data. Repairs are attempted and characterized. In the end, the impact of native defects is discussed along with the viability of various repair methods.

The defectivity challenges of extreme ultraviolet (EUV) masks, that need to be addressed before production readiness of EUV lithography is assured from the mask perspective, are twofold. First, the EUV-specific defect type relating to the multi-layer (ML) mirror, the so-called ML-defects, require to become more detectable than they are printable. This not only requires proven capability of blank inspection, but also the existence of satisfactory printability mitigation strategies (comprising avoidance, pattern shift methodology, compensation repair). Both these assets need to become available within the mask supply chain, as there is little that can still be done about such residual defects at the wafer fab. In a production phase, finding unexpected printing ML-defects is unacceptable. It is shown how the specific way-of-working in use at imec, starting from the printed wafer, contributes to related learning and identification of remaining gaps, in getting this issue fully dealt with. The second challenge relates to particle contamination during use of the reticle at the wafer fab. Avoiding overlaycritical particles on the backside of NXE3100 reticles is facilitated by the established way-of-working. Minimizing the occurrence of particles “hopping” between reticles via the electrostatic clamp of the scanner (so-called clamp-traveling particles) is a major driver for appropriate mask cleaning. The latter may not have negative impact by frequent use, in view of the highly vulnerable EUV mask stack, and especially for the present “black-border” solution in which the ML is etched away at the image border on the reticle. A lot of effort is spent into monitoring of NXE3100 reticles for particle adders on the pattern side. This is realized by comparing past and present mask defect maps obtained by inspection of printed wafers with subsequent repeater analysis.

The framework and the current status of a newly developed PEM pattern inspection system are presented. A die-to-die defect detection sensitivity of the developing system is investigated. A programmed defect mask was used for demonstrating the performance of the system. Defect images were obtained as difference images by comparing the PEM images “with-defects” to the PEM images “without-defects”. The image-processing system was also developed for dieto- die inspection. A targeted inspection-throughput of 19-hour inspection per mask with 16 nm pixel size for image capture was attained. Captured images of extrusion and intrusion defects in hp 64 nm L/S pattern were used for detection. Then 16 nm sized intrusion defect, which was our target size for hp 16 nm defect detection requirement, was identified without false defects. To improve the performance of hp 16 nm patterned mask inspection, defect detection requirements for hp 11 nm EUVL patterned mask inspection was studied.

Five EUV film stacks were prepared and evaluated from the multiple viewpoints of mask repair process: etching property, CD control and wafer print. Etching property results revealed a thicker lower reflective (LR) layer stack showed good performance. Some types of defects were repaired and a CD comparison done with both CD-SEM and EUV microscope. It was found thinner total film stack (LR plus absorber) performs better than thicker ones for CD control. In addition, thicker LR performed better than thinner LR. Wafer print performance on the repaired site was evaluated through focus by imaging on an EUV microscope. Wafer printability performance showed that thinner total film stack performed better than a thicker one. Finally the best stack for EUV mask repair performance was determined to be a thinner total film stack and thicker a LR from all the various points of view.

While extreme ultraviolet lithography (EUVL) is the leading candidate of the next generation lithography, the challenge of managing blank defects must be overcome before EUVL being put to practical use. Besides the efforts of manufacturing defect free blanks, the use of mitigation technique called “pattern shift” is now considered to be a more feasible solution. Whether we aim for defect free blanks or use pattern shift, however, it is quite important to understand the properties of the defects on EUV masks. Of particular interest is to distinguish phase defects from amplitude defects, and pits from bumps. To address the need to understand defect properties, the Actinic Blank Inspection (ABI) high volume manufacturing (HVM) model has acquired a review function using a 1200x magnification optics capable of accurately measuring the size and shape of defects. In this paper, we will discuss how the ABI HVM model classifies defects into pits and bumps.

A high-volume manufacturing (HVM) actinic blank inspection (ABI) prototype has been developed, of which the inspection capability for a native defect was evaluated. An analysis of defect signal intensity (DSI) analysis showed that the DSI varied as a result of mask surface roughness. Operating the ABI under a review mode reduced that variation by 71 %, and therefore this operation was made available for precise DSI evaluation. The result also indicated that the defect capture rate was influenced by the DSI variation caused by mask surface roughness. A mask blank was inspected three times by the HVM ABI prototype, and impact of the detected native defects on wafer CD was evaluated. There was observed a pronounced relationship between the DSI and wafer CD; and this means that the ABI tool could detect wafer printable defects. Using the total DSI variation, the capture rate of the smallest defect critical for 16 nm node was estimated to be 93.2 %. This means that most of the critical defects for 16 nm node can be detected with the HVM ABI prototype.

Etched multilayer masks in EUV lithography for 16 nm node and below are better than conventional binary masks due to their higher image intensities and image slopes. However, aerial-image simulation of etched multilayer masks requires special care in order to obtain accurate results. In this paper, we first show that the usual Hopkins method for partial coherence simulation gives very inaccurate results when off-axis illumination is used. We then discuss an enhanced Hopkins method which provides far greater accuracy. Simulation results are presented to demonstrate the importance of using the enhanced Hopkins method for EUV lithography simulation.

The main problem in extreme ultra-violet (EUV) lithography for mass production is low source power. In order to overcome this problem, we suggest to use an etched multilayer mask introduced several years ago. The etched multilayer mask structure does not need an absorber stack and it was found that we could get higher aerial image slope and peak intensity than those of the conventional absorber mask structure. Also, the etched multilayer mask can reduce the pattern shift and horizontal-vertical (H-V) bias.

To satisfy the requirement on the image placement accuracy, it is very important to consider the stress of the films on the mask substrate. The stress of the EUV mask is much larger than several kinds of optical masks because reflective Mo/Si multilayer (ML) has large compressive stress. In recent years, thinner absorber has been proposed because of better resolution and less shadowing effect. However it results in the leakage of the light to the adjacent chips on wafer. Then the light shield around the pattern area on the mask has been developed. From the viewpoint of manufacturability, etched multilayer black border (BB) is advantageous. Pattern displacement occurs at the edge of the multilayer etched BB. Measured pattern displacement error increased near the BB and it was simulated by using finite element method. The displacement depends strongly on the ML stress and it is successfully described by the release of the compressive stress at the edge of the black border. Most of the deformation near the BB remains even if the mask is chucked to the flat surface. Simulation using various models are discussed and compared with experimental results.

In order to realize EUV mask pattern defect inspection in 16nm node, we have developed a new inspection system assembled with a new optical system on novel projection electron microscopy (PEM) and a new mask handling and imaging system, e.g., a high precision stage, an imaging detector, an image processing system, and so. on. This inspection system enables us to make the inspection in high resolution and high speed as compared to conventional DUV and EB inspection systems. In this paper, we describe the performance evaluation as concerning to the acquisition operation on the assembled new inspection system with 16nm node EUV mask: 1) Still and TDI image acquisition, and 2) die-to-die inspection. The results show that the new inspection system operations in the still and TDI modes are in much feasibility in stable image acquisition, and in the die-to-die inspection are capable to execute the die-to-die inspection for 1Xnm EUV mask.

Recently there has been a demand for high durability MoSi masks. There are some candidates for MoSi mask materials. They are preferable for both mask user and mask manufacture because they show not only high durability against exposure or cleaning process but also process compatibility in production line[1]. They are gaining momentum to practical application. However, there is a drawback for manufacturing regarding the mask repair process. Because ebeam repair employs pure chemical reaction, it faces severe etching difficulty due to higher chemical stability. Meanwhile, the tool supplier has looked into that chemical reaction in detail since the problem was unveiled. They developed a dedicated etching process for high durable materials. It’s so important for the mask manufacturer to evaluate this process properly before they transfer conventional MoSi to new high durability MoSi. A comprehensive understanding of this new process should be acquired by trying several kinds of etching tests. In this paper we will report the results ranging from basic etching rate, selectivity, repair accuracy to flexibility for complicated shaped defects. This data tells us a lot about if it can be applied for practical use. The experiment was performed with e-beam repair tool “MeRiT^Ⓡ”, which was released as the latest version from ZEISS last year. An improved new etching process was applied to “A6L2” type high durable blanks provided by HOYA corporation. A wide variety of programmed defects were arranged on a line and space featured test mask. These programmed defects were repaired with the procedure developed by ZEISS. After repair, printed image was evaluated by AIMS^TM system. This paper will discuss the initial results of these first steps into the uncharted territory of high durability MoSi repair.

In advanced semiconductor manufacturing, model-based optical proximity correction is commonly used to compensate for image errors. The final pattern is generated using correction values determined by lithography simulation. Image errors such as patterns with insufficient correction or patterns with excessive correction can be generated. These patterns with errors are called hotspots. Such errors are conventionally detected by lithography simulation of OPC patterns. When a hotspot is detected by lithography simulation, it has to be repaired manually or by repeated use of OPC tool. However, it is difficult to obtain correct pattern for a complicated shape, and the correction procedure may require a significant amount of additional processing. In order to solve this issue, we examine application of cellular automata (CA) method for hotspot correction. It is known that CA method can be used for weather or traffic analysis and prediction. In this report, we studied the CA method for deriving simple hotspot repair rule based on lattice cell-like models for light intensity distribution and OPC patterns. We will report on the results of hotspot correction technique with the OPC pattern using CA method.

For 193 nm immersion lithography, it is hard to print clear 4X nm dense images (ex. contact holes) on wafer without any modifications due to lower light intensity. In the past, the most common method is to add the scattering bars, which can enhance the light intensity of contact holes. However, with tinier pattern, the distance between scattering bars and contact holes will get quite close. Hence, the error tolerance for mask making was reduced. On the other hand, this method may also cause the pattern twist which will induce pattern crosslink. To solve this issue, a new design method for lithography mask was proposed, which is named “Phase-shifting Scattering Bar”, and it shows better performance in 1D chain array patterns than those with traditional scattering bars. However, for even tinier patterns, it is quite difficult to put these scattering bars on mask. Hence, another special design named “Interlaced Phase-shifting Mask” was proposed to handle such tiny dense patterns. In this design, main patterns are also the scattering bars for adjacent patterns. Hence, there is no need for additional tiny scattering bars, and the mask making requirement can be also relaxed. Both of these two mask design are useful tools to trim and modify light intensity profile on wafer. The image contrast was largely enhanced which means a better resolution and a larger process window can be gained without the cost of new illumination equipments.

In this paper we study the trade-offs and benefits of using ILT-based SRAF placement/OPC over conventional SRAF placement/OPC for various front-end and back-end design configurations on a full chip. We explore the use models and benefits of using ILT-based Local Printability Enhancement (LPE) in an automated flow to eliminate hot spots that can be present on the full chip after conventional SRAF placement/OPC. We study the impact on process-window, performance, and mask manufacturability.