4.1.

ADC and DAC

The effective number of bits (ENOB) of ADC and DAC needs to be well considered so as not to be the dominant noise source. The conservative requirement to the ENOB comes from the quantization noise as well as the clipping noise, which is an additional noise term due to the clipping when the amplitude of superimposed tones exceeds the maximum range of the ADC and DAC. The SNR is given as¹⁰

In this study, we do not specify any particular ADC because there is no such a commercially available space-grade ADC that satisfies the ENOB requirement at this time. There are some nonspace grade ADCs with the ENOB of 11 bits or higher, such as Texas Instruments ADS54J40, which is a dual-channel 14-bit 1 Gsps ADC with $1.35\mathrm{W}/\text{channel}$ power dissipation. For this study, we only assume the number of bits and power for ADC as 14 bits and 1 W at 1 Gsps. For the DAC, Texas Instruments DAC5670-SP is available, which is a dual-channel 14-bit 2.4 Gsps (or 1.2 Gsps per channel) space-grade DAC. The power dissipation for this DAC is 2 W or $1\mathrm{W}/\text{Channel}$ at 1 Gsps.

4.2.

FPGA Design

Although the 1-GHz RF block is the common design for three TES arrays, the FPGA firmware design of DEEP needs to be tailored for each TES array since the number of multiplexed channels per HEMT is different. The main design of the firmware is the same as in Ref. 11 with a few exceptions. In this design, we use a polyphase filter bank (PFB) channelizer¹² on both the tone generation and the channelization, and the FFT size of the PFB channelizer depends on the type of array. Table 4 shows the summary of three TES arrays along with the FFT size.

Table 4

The summary of three TES arrays and the required number of each component.

Figure 4 shows the FPGA firmware block diagram. The 500-MHz clocked part on the left is a parallel PFB coarse channelizer that takes a 1-Gsps $I/Q$ data stream from the ADC and splits it into 128/32/256 channels. The other 500-MHz clocked part on the right is another parallel PFB channelizer that generates the frequency comb. The 250-MHz clocked center parts are four demodulators that perform the flux-ramp demodulation and one event processor that performs triggering and optimal filtering.

Fig. 4

The FPGA firmware block diagram. The 500-MHz clocked part on the left is a parallel coarse channelizer that takes 1-Gsps I/Q data stream from ADCs and splits into 32/128/256 channels. The other 500-MHz clocked part on the right is a parallel dechannelizer that generates the input frequency comb. The 250-MHz clocked center parts are four demodulators that perform the flux-ramp demodulation and one event processor that performs triggering and optimal filtering.

4.2.1.

Tone generation and channelization

The channelizer consists of PFB blocks and FFT blocks. The PFB in this design is implemented as an eight-tap finite impulse response (FIR) filter. All blocks in the channelizer are driven with a 500-MHz clock, and two PFBs and two FFTs are in parallel to process the 1-GHz $I/Q$ data streams. The FFT size is equal to the number of resonators (or sensor channels) per 1-GHz bandwidth rounded up to the next power of two: e.g., 128 for the main array, 32 for the enhanced main array, and 256 for the ultra-high-resolution array.

Since the resonator spacing and the FFT bin frequency width do not match, the PFB channelizer needs to handle an arbitrary frequency tone. Figure 5 shows the frequency response of the PFB. The solid line shows the single-bin frequency response, and dashed lines show the responses of neighboring bins. To prevent the signal leakage and the scalloping loss, the pass-band of this PFB is limited to the red-shaded range, which is $\pm 30\%$ of the FFT bin width from the bin center, and therefore, one PFB channelizer only covers 60% of 1-GHz bandwidth. There is an additional PFB channelizer to cover the rest of the bandwidth. For the tone generation, it is followed by a frequency shifter that shifts the signal frequency by the half of the FFT bin width, and the frequency-shifted signal is summed with the signal from the first PFB channelizer, as shown in the bottom half of Fig. 4. For the coarse channelization, the additional channelizer receives the $I/Q$ signals that are frequency shifted by the same amount.

Fig. 5

The frequency response of the PFB. The solid line shows the single-bin frequency response and dashed lines show the frequency responses of neighboring bins ($\pm 1$ and $\pm 2\text{bins}$). The red-shaded regions are pass-bands, which is $\pm 30\%$ of the bin width from the bin center.

The signals from the two PFB channelizers are interleaved and serialized as a single $1/N_{\mathrm{FFT}}$ GHz signal stream for each channel, where $N_{\mathrm{FFT}}$ is the number of the FFT size, and given to a channel select, which is a multiplexer that the following demodulators can select a channel from. On the other side, another channel select receives signals from the demodulators and sends it to a deserializer. The deserializer parallelizes the incoming signals to the parallel FFTs.

4.2.2.

Microwave SQUID multiplexer demodulator

The demodulators, which are shown at the center part in Fig. 4, are to demodulate the flux-ramp modulation. These are four identical blocks and run in parallel driven with a 250-MHz clock. One demodulator can process up to $N_{\mathrm{FFT}}$/4 channels, and it receives the channelized $I/Q$ data streams from the PFB channelizer and extracts the sensor signal for each channel. Figure 6 shows the block diagram of the demodulator. The demodulated sensor signals are fed into the event processor, which is described later.

Fig. 6

The block diagram for the 250-MHz clocked flux-ramp demodulator.

Following the diagram in Fig. 6, the signal from the coarse channelization comes from the left into the channel select. Since this signal is in an intermediate frequency, it needs to be mixed down to zero intermediate frequency at the first $I/Q$ mixer stage in the demodulator for fine-tuning. The LO for the mixer is implemented using a direct digital synthesizer (DDS). There are two independent DDSs (one for $I$ and one for $Q$) to allow to compensate for phase deviations from the ideal 90-deg phase difference for $I$ and $Q$ of the analog demodulators in the RF electronics.

In addition to the DDSs used for the LO, there are two additional DDSs that generate the same frequency $I/Q$ tones as for the $I/Q$ mixer. Those tones are passed to the PFB channelizer for the tone generation via the channel selector. The channelizer DDSs are also independent synthesizers to allow for phase adjustment to compensate for phase deviations of the $I/Q$ modulators in the RF electronics.

The fine-tuned $I/Q$ baseband signals are then low-pass filtered using a 16-tap FIR filter to reject spurious tones outside the bandwidth of the resonator. At this point, the baseline signals draw an arc in the $I/Q$ complex plane, and the angle of the arc represents the sensor signal with the flux-ramp modulation.¹¹ We use a coordinate rotation digital computer¹³ (CORDIC) block to calculate the arc angle, but the arc needs to be first centered at the origin and rotated to the positive $x$-axis. The arc center is fit in advance and subtracted to translate the arc to the origin. Another CORDIC is then used to rotate the arc, and the angle is calculated using the CORDIC taking the arctangent of the $I/Q$ signals.

Finally, the demodulation of flux-ramp modulation is performed. This process involves another $I/Q$ mixing with sinusoids generated by a DDS, masking a transient caused by the flux-ramp reset, integrating the mixed signals over the integer number of mixing frequency periods, and calculating the angle of the $I/Q$ signals after the integration taking the arctangent using a CORDIC.¹¹ At this point, the data rate is reduced to the flux-ramp frequency per each channel. One final step in the demodulation stage is phase unwrapping to linearize the periodical phase signal from the last CORDIC.

4.2.3.

Event processing

The event processor, which is shown at the bottom center in Fig. 4, captures demodulated sensor signals from four demodulators and extracts the incident x-ray photon energy. It is also driven with the 250-MHz clock. Figure 7 shows the block diagram of the event processor.

Fig. 7

The block diagram for the 250-MHz clocked event processor. The pixel differentiation (hydra demux) and the decimation are only for the main array and the enhanced main array.

The event processor triggers on x-ray pulses and extracts the pulse records from the stream of the sensor signal. The trigger block consists of a derivative, which calculates the difference from the previous data point for each channel, and an edge trigger, which triggers when the incoming signal crosses the given threshold in the given direction (up or down). With the combination of these two, this block behaves as a simple slope trigger for the incoming signal from the demodulator. For the triggered signal, the rise-time of the pulse is measured and used to differentiate the $5\times 5$ hydra pixel for the main array and the enhanced main array. Furthermore, the pixel differentiated signal is decimated by a factor of 4 using a cascaded integrator-comb filter.¹⁴ The pixel differentiation and the decimation are not performed for the ultra-high-resolution array. The signal is then supplied into a pretrigger delay, which is a circular buffer implemented using a block RAM, and the stored signal is taken out from the other side after a certain amount of delay.

The optimal filtering block performs optimal filtering and event grading. We are assuming Suzaku and Hitomi-style grading.^15,16 There are three event grades, high resolution (HR), medium resolution (MR), and low resolution (LR), based on two-time differences: $\mathrm{\Delta }{t}_{\mathrm{p}}$, which is the time between the previous trigger and the current trigger, and $\mathrm{\Delta }{t}_{\mathrm{n}}$, which is the time between the current trigger and the next trigger. For each $\mathrm{\Delta }{t}_{\mathrm{p}}$ and $\mathrm{\Delta }{t}_{\mathrm{n}}$, two thresholds are given, and if an event occurs with both $\mathrm{\Delta }{t}_{\mathrm{p}}$ and $\mathrm{\Delta }{t}_{\mathrm{n}}$ exceeding the strict thresholds, the event is graded as HR. If both $\mathrm{\Delta }{t}_{\mathrm{p}}$ and $\mathrm{\Delta }{t}_{\mathrm{n}}$ are less than the relaxed thresholds, the event is graded as LR. All other events are graded as MR. For HR and MR events, optimal filtering is performed. For LR events, optimal filtering is not performed, but the signal is integrated for a certain number of data points after the offset of the signal is subtracted. These calculations are speculatively executed in parallel, and at the same time the event is graded based upon $\mathrm{\Delta }{t}_{\mathrm{p}}$ and $\mathrm{\Delta }{t}_{\mathrm{n}}$. Once the event is graded, the corresponding result is selected, and other two results are discarded. Moreover, because these calculations are continuously executed without a dead time for the incoming x-ray pulse events, the upper limit on count rate in the readout hardware will be equal to the theoretical limit, which is the inverse of the shortest LR record length.

Each HR and MR optimal filtering performs three optimal filtering at the same time, one with an event record delayed by one data point, one with an event record with no delay, and one with an event record advanced by one data point. These three values are later used to interpolate the maximum pulse height after fitted with a quadratic function. This interpolation is not assumed to be performed in the firmware for this study.

The templates for optimal filtering are stored in a block RAM to perform multiple filtering in parallel, and the maximum number of templates that can be stored in the block RAM is hence limited. For the $5\times 5$ hydra arrays, 25 templates are assumed for each hydra pixel, and they are shared with all the TESs within the 1-GHz RF block. For the nonhydra array, one template per TES is assumed. For HR events, a full-length template is used, while a quarter-length template is used for MR events. The template length, or record length, for each array, is chosen so that the record length is longer than $10{\tau }_0$, where ${\tau }_0$ is the TES pulse decay time constant. The record length for LR is 1/16 of the full length. Table 5 summarizes the sampling rate and record length for each TES array type.

Table 5

Sampling rate and record length for each array type.

	Main array	Enhanced main array	Ultra-hi-res array
TES ${\tau }_0$	2.7 ms	0.67 ms	0.32 ms
Sampling rate	500 ksps	2 Msps	300 ksps
Rate after decimation	125 ksps	500 ksps	—
Record length
HR	$4096\mathrm{pts}/32.8\mathrm{ms}$	$4096\mathrm{pts}/8.2\mathrm{ms}$	$1024\mathrm{pts}/3.5\mathrm{ms}$
MR	$1024\mathrm{pts}/8.2\mathrm{ms}$	$1024\mathrm{pts}/2.0\mathrm{ms}$	$256\mathrm{pts}/0.8\mathrm{ms}$
LR	$256\mathrm{pts}/2.0\mathrm{ms}$	$256\mathrm{pts}/0.5\mathrm{ms}$	$64\mathrm{pts}/0.2\mathrm{ms}$
Pretrigger length
HR	$255\mathrm{pts}/2.0\mathrm{ms}$	$255\mathrm{pts}/0.5\mathrm{ms}$	$63\mathrm{pts}/0.2\mathrm{ms}$
MR	$63\mathrm{pts}/0.5\mathrm{ms}$	$63\mathrm{pts}/0.1\mathrm{ms}$	$15\mathrm{pts}/50\mu \mathrm{s}$
LR	$31\mathrm{pts}/0.2\mathrm{ms}$	$31\mathrm{pts}/60\mu \mathrm{s}$	$7\mathrm{pts}/23\mu \mathrm{s}$

4.3.

FPGA Resource Estimation

For a high-performance signal processing and computation in space, the space-qualified Xilinx Virtex-5QV has been used with success in many projects since 2011. Although it will still be used in some of the near-term missions planned to launch around 2020, the resource availability of Virtex-5QV is quite limited if compared with the recent newer-generation resource-rich FPGAs. To replace Virtex-5QV for the next decade, Xilinx is now space qualifying the Zynq UltraScale+ MPSoC, and it is expected to be rolled out in 2019. For the Lynx mission, we are baselining using the space-qualified MPSoC, RT-ZU19EG, and in this section, we estimate the resource and power usage for the firmware described in the previous section. In addition to MPSoC, the estimation is performed for Xilinx UltraScale+ RFSoC and defense-grade Virtex-5Q for comparison. The RFSoC is an FPGA Xilinx recently released, and it has the same architecture as MPSoC but has some integrated high-speed ADCs and DACs. It is well suited to the microwave SQUID multiplexing readout, but it is not expected to be space-qualified. The defense-grade Virtex-5Q has a flight legacy at NASA, and it is a backup option to MPSoC. The space-grade Virtex-5QV does not have enough resources, and it is excluded from the estimation. Table 6 summarizes the available resources for MPSoC, RFSoC, Virtex-5Q, and Virtex-5QV.

Table 6

The summary of available resources for FPGA candidates.

For a better resource estimation, we have developed most of the firmware and synthesized using Xilinx ISE and Vivado and checked the resource usage for a single 1-GHz RF block. Table 7 shows the estimated resource usage on look-up tables (LUT), flip-flops, digital signal processing (DSP) cores, and 36k-bit block RAM blocks for the Virtex-5 family and the UltraScale+ family. We used the Xilinx ISE Design Suite 14.6 for Virtex-5 and the Xilinx Vivado Design Suite 2016.4 for UltraScale+. Note that this is not a resource usage after the actual mapping on specific device resources, so the estimation is still approximate. Moreover, the $I/O$ pin availability was intentionally left out in this study, as we have not chosen the specific ADCs and DACs at this stage.

Table 7

Estimated resource usage per 1-GHz process block.

The required number of FPGAs per HEMT was calculated based on the number of 1-GHz RF blocks that can be fitted into a single FPGA. Figure 8 shows the total resource usages on MPSoC, RFSoC, and Virtex-5Q for the various number of FPGAs per HEMT. During this study, one UltraRAM, which is only available in MPSoC and RFSoC, was treated as eight 36k-block RAM blocks. The top, middle, and bottom rows show the usages for the main array, enhanced main array, and ultra-high-resolution array, respectively. The dashed line in the plots shows the 80% threshold.

Fig. 8

The FPGA resource usages for the various number of FPGAs per HEMT. The dashed line in the plots shows the 80% threshold.

For the main array, if using MPSoC or RFSoC, a single FPGA is required per HEMT, alternatively, if using Virtex-5Q, four FPGAs are required per HEMT. Similarly, for the enhanced main array, the required number of FPGAs per HEMT is 1 for the MPSoC case, 0.5 for the RFSoC case, and 2 for the Virtex-5Q case. Finally, for the ultra-high-resolution array, it is on FPGA per HEMT for the MPSoC case, two for the RFSoC case, and four for the Virtex-5Q case.

4.4.

Power and Mass Estimation

Based on the estimated resource usage, we calculated the FPGA unit power using the Xilinx Power Estimator. The power estimation largely depends on the toggle-rate, which is signal transitions per clock cycle, but it is not easy to accurately estimate the rate. According to Xilinx, 12.5% is the default value, and most of the logic-intensive designs work at around this rate, while 20% can be used for the worst-case estimate.¹⁷ For arithmetic-intensive designs, 50% represents the absolute worst case. For this study, we used 25% of toggle-rate for the 500-MHz clocked devices as they are more arithmetic-intensive modules, and 12.5% of toggle-rate for the 250-MHz clocked devices as they are a mix of logic and arithmetic operations. For the $I/O$ interface to the external ADC and DAC, we assumed 500-MHz double data rate low voltage differential signaling for each 1 Gsps ADC and DAC with the bit widths of 14 bits.

Table 8 shows the estimated FPGA unit power for each type of array together with the required number of FPGAs and the total FPGA power. Note that the actual number of RFSoC FPGAs for the enhanced main array will be one greater than shown due to the need to round up to an integer number of FPGAs per box, but for the power estimation, we did not round up the number as the power nearly scales with the resource usage not the number of FPGAs.

Table 8

Estimated FPGA power for each type of array.

In addition, the power for the bias and flux-ramp generator needs to be estimated. For the TES bias, one 12-bit low-speed DAC per HEMT is assumed, and for the flux-ramp signal, one 12-bit medium-speed ($<10\mathrm{Msps}$) DAC is assumed. The logic to generate these signals is very simple and does not require much FPGA resource. Although it may be possible to include the logic into the Xilinx FPGA, we assume a separate PCB with a single Microsemi RTAX2000 FPGA for each box. The estimated power is 4 W per board.

Table 9 shows the estimated power for the DEEP in two observation modes: (A) an observation with the main and enhanced main arrays and (B) an observation with the ultra-high-resolution array. For ADC and DAC power, 16 W per HEMT was assumed for eight of each 1-Gsps ADC and DAC, 1 W for each, as described in a previous section. The power shown for the power card is a power loss assuming 80% efficiency. Using the MPSoC baseline design, the estimated maximum power dissipation for the DEEP is 615 W or $308\mathrm{W}/\text{box}$. The same for the RFSoC case is 284 W or $142\mathrm{W}/\text{box}$, and for the Virtex-5Q case, it is 995 W or $498\mathrm{W}/\text{box}$.

Table 9

Estimated power for the DEEP in two observation modes.

The housing for the DEEP is a modular housing with a backplane, with the standard PCB size of $8\mathrm{in.}\times 10\mathrm{in.}$ The number of PCBs per box for the MPSoC baseline design is $14:1$ PCB for the bias and flux-ramp generator, 11 PCBs for the signal processing FPGA and ADC/DAC (5 for the main array, 3 for the enhanced main array, and 3 for the ultra-high-resolution array), and 2 PCBs for the power card. For the signal processing PCB, one FPGA per PCB was assumed. The mass estimate for the standard PCB is 0.7 kg, but an additional thermal conductive layer needs to be added to the signal processing PCB and the power card PCB, which makes 30% increase in PCB mass (0.9 kg). The housing size was estimated as $15.5\mathrm{in.}\times 11.5\mathrm{in.}\times 9.5\mathrm{in.}$ with a mass of 10.2 kg. The backplane mass was estimated at 1.5 kg. Table 10 shows the summary of the size and mass for the DEEP, and the estimated total mass is 48.2 kg or $24.1\mathrm{kg}/\text{box}$. Figure 9 shows the summary of the estimated number of each component, and the estimated size, mass, and the maximum power for each RF electronics and DEEP box.

Table 10

Estimated size and mass for the DEEP.

Fig. 9

The summary of the estimated number of each component, and the estimated size, mass, and the maximum component power for each RF electronics and DEEP box. The power card and bias/flux-ramp generator card are omitted in the DEEP box diagram.

5.1.

Tone Tracking

Microwave SQUID multiplexers utilize warm readout electronics to digitally generate a comb of RF tones to probe the individual microwave SQUID channels. The noise performance and stability of microwave SQUID multiplexing systems can be enhanced with tone tracking electronics, which actively adapt the probe frequency to follow the changing resonance frequencies due to both the flux-ramp modulation and the x-ray pulses.

Most existing warm electronics, including the one in this study, read out superconducting resonators using RF probe tones that are fixed at the central frequency of the phase-modulated resonances. Even for an RF system that only generates tones in less than an octave of bandwidth, nonlinearities in broadband components in the signal path will generate unwanted third-order intermodulation products that will fall directly in-band. The theoretical number of third-order tones generated in an $N$ tone system is $2N(N-1)$. For example, in a readout generating 2000 tones, nearly 8 million third-order intermodulation products will be produced, with the power in these tones growing as the cube of the power in the fundamental tones. For large multiplexing factors and sufficiently high power, the intermodulation products become an irreducible pseudonoise floor. Certain intermodulation products can also produce unwanted crosstalk.

More advanced room-temperature electronics can instead track the shifting resonator frequencies and maintain each probe tone on resonance using a closed feedback loop operating independently on each tone.¹⁸ Tone tracking can reduce the transmitted power as much as 20 dB, greatly diminishing third-order modulation products, because, when perfectly on resonance, most of the power is reflected off the resonator, rather than transmitted forward to the amplifier.

The advanced tone-tracking algorithms that have been implemented in the SLAC Microresonator RF electronics¹⁸ have low computational resource needs in electronics FPGAs or ASICs, and are therefore compatible with a satellite platform, although this has not been baselined for the Lynx readout. This reduction has potential advantages improving noise, reducing crosstalk, and allowing for a reduction in bias power to the broadband components in the readout chain, improving the engineering margins for a satellite system.

5.2.

Resource Reduction

It is interesting to consider different methods in which the resource requirement of this system can be reduced in future studies. These resources will include, but not be limited to, size, mass, and power. For example, to reduce mass and size, we can consider higher-bandwidth components. In this study, we notionally split the 4-GHz bandwidth to four 1-GHz subbands and performed several estimates. We are optimistic about the availability of higher-bandwidth components, such as a 2-GHz ADC, that are, or can be, space-qualified in the near future. In this case, it would be possible to reduce the number of LOs, $I/Q$ modulators/demodulators, ADCs, and DACs by half. Although the estimated power for the RF electronics and DEEP would not be reduced greatly, it would be a significant mass and size reduction for the RF electronics. In addition, the reduction in the number of ADCs and DACs would help to simplify the design of the signal processing PCB which would, as a result, lower the design costs and improve the reliability.

Another example is if the UltraScale+ RFSoC can be space qualified. As discussed in Sec. 4.4, the DEEP power would then be reduced almost by half, and it would lower the total power consumption from 756 to 425 W.

5.3.

Thermal Loading and Radiation Hardness

As strict requirements for the Lynx do not exist at this point, the thermal loading and radiation hardness of the designed system are not addressed in this study. The component power values used in this study are typical values taken from their datasheets or official power estimators. The component temperature was assumed at room temperature. In the FPGA firmware design, no mitigations were incorporated for single-event phenomena, such as single-event upsets and single-event transients. At this point, these are beyond the scope of this paper, but we hope to address them in future work.